Linear regulator with improved power supply rejection ratio

Abstract

A linear regulator with a pass device having a first terminal, a second terminal and a drive terminal is presented. The first terminal of the pass device is coupled with the supply voltage of the linear regulator. The second terminal of the pass device is coupled with the output of the linear regulator. A driver stage is coupled with the supply voltage of the linear regulator, and the drive terminal of the pass device drives the pass device with a driving voltage. A compensating circuit compensates for a change in a voltage difference between the drive terminal of the pass device and the supply voltage of the linear regulator.

What is claimed is: 
     
       1. A linear regulator comprising: a pass device having a first terminal, a second terminal and a drive terminal, the first terminal of the pass device coupled with the supply voltage of the linear regulator, the second terminal of the pass device coupled with the output of the linear regulator; a driver stage coupled with the supply voltage of the linear regulator and the drive terminal of the pass device to drive the pass device with a driving voltage; and a compensating circuit configured to compensate for a change in a voltage difference between the drive terminal of the pass device and the supply voltage of the linear regulator; wherein the driver stage comprises a drive transistor, the compensating circuit comprises at least one further drive transistor, a. wherein the drive transistor of the driver stage is in a current mirror configuration with the pass device; b. wherein the drive transistor of the driver stage is arranged in parallel with the at least one further drive transistor of the compensating circuit; wherein the compensating circuit further comprises at least one low-pass filter (LPF) coupled between the drive transistor and the at least one further drive transistor, wherein the at least one LPF corresponds to the at least one further drive transistor; and wherein the driver stage further comprises a first transistor, each of the drive transistor and the at least one further drive transistor further comprising a second terminal, wherein the second terminal of each of the drive transistor and the at least one further drive transistor is directly coupled with the first transistor. 
     
     
       2. The linear regulator of  claim 1 , wherein:
 a. each of the drive transistor and the at least one further drive transistor comprises a first terminal and a drive terminal; 
 b. the first terminal of each of the drive transistor and the at least one further drive transistor is coupled with the supply voltage of the linear regulator; and 
 c. the drive terminal of the drive transistor is coupled with the drive terminal of the pass device, the drive terminal of the drive transistor providing the driving voltage to drive the pass device. 
 
     
     
       3. The linear regulator of  claim 2 , wherein each of the at least one LPF comprises an input and an output, the input of each LPF coupled to the drive terminal of the drive transistor, the output of each LPF coupled to the drive terminal of the corresponding further drive transistor. 
     
     
       4. The linear regulator of  claim 1 , wherein the at least one LPF has a transfer function with poles. 
     
     
       5. The linear regulator of  claim 1 , wherein some of the at least one LPF have a transfer function with poles and zeros. 
     
     
       6. The linear regulator of  claim 1 , wherein the compensating circuit comprises N low-pass filters (LPFs) and N further drive transistors, where N is an arbitrary integer. 
     
     
       7. The linear regulator of  claim 6 , wherein N corresponds to a number of LPF cut-off frequencies at which the change in the voltage difference between the drive terminal of the pass device and the supply voltage of the linear regulator is compensated. 
     
     
       8. The linear regulator of  claim 1  wherein: a. the first transistor comprises an NMOS transistor; b. the drive transistor comprises a PMOS transistor, the first terminal of the drive transistor comprising a source terminal of the PMOS transistor, the drive terminal of the drive transistor comprising a gate terminal of the PMOS transistor; c. the at least one further drive transistor comprises at least one further PMOS transistor, the first terminal of the at least one further drive transistor comprising a source terminal of the at least one further PMOS transistor, the drive terminal of the at least one further drive transistor comprising a gate terminal of the at least one further PMOS transistor; and d. the voltage difference between the drive terminal of the pass device and the supply voltage of the linear regulator is associated with a voltage difference between the gate and the source terminal of the PMOS transistor of the driver stage. 
     
     
       9. The linear regulator of  claim 1 , wherein the pass device comprises a PMOS transistor. 
     
     
       10. The linear regulator of  claim 1 , further comprising:
 a. a first amplifier stage; 
 b. a second amplifier stage coupled between the first amplifier stage and the driver stage; and 
 c. a capacitor coupled between the first amplifier stage and the output of the linear regulator. 
 
     
     
       11. The linear regulator of  claim 1 , wherein the driver stage comprises a buffer stage. 
     
     
       12. A method of providing a linear regulator comprising the steps of: providing a pass device having a first terminal, a second terminal and a drive terminal, the first terminal of the pass device coupled with the supply voltage of the linear regulator, the second terminal of the pass device coupled with the output of the linear regulator; providing a driver stage coupled with the supply voltage of the linear regulator and the drive terminal of the pass device to drive the pass device with a driving voltage; and providing a compensating circuit to compensate for a change in a voltage difference between the drive terminal of the pass device and the supply voltage of the linear regulator; wherein the driver stage comprises a drive transistor, the compensating circuit comprises at least one further drive transistor, a. wherein the drive transistor of the driver stage is in a current mirror configuration with the pass device; b. wherein the drive transistor of the driver stage is arranged in parallel with the at least one further drive transistor of the compensating circuit, and wherein the compensating circuit further comprises at least one low-pass filter (LPF) coupled between the drive transistor and the at least one further drive transistor, wherein the at least one LPF corresponds to the at least one further drive transistor; and wherein the driver stage further comprises a first transistor, each of the drive transistor and the at least one further drive transistor further comprising a second terminal, wherein the second terminal of each of the drive transistor and the at least one further drive transistor is directly coupled with the first transistor. 
     
     
       13. The method of  claim 12 , wherein:
 a. each of the drive transistor and the at least one further drive transistor comprises a first terminal and a drive terminal; 
 b. the first terminal of each of the drive transistor and the at least one further drive transistor is coupled with the supply voltage of the linear regulator; and 
 c. the drive terminal of the drive transistor is coupled with the drive terminal of the pass device, the drive terminal of the drive transistor providing the driving voltage to drive the pass device. 
 
     
     
       14. The method of  claim 13 , wherein each of the at least one LPF comprises an input and an output, the input of each LPF coupled to the drive terminal of the drive transistor, the output of each LPF coupled to the drive terminal of the corresponding further drive transistor. 
     
     
       15. The method of  claim 12 , wherein the at least one LPF has a transfer function with poles. 
     
     
       16. The method of  claim 12 , wherein some of the at least one LPF have a transfer function with poles and zeros. 
     
     
       17. The method of  claim 12 , wherein the compensating circuit comprises N low-pass filters (LPFs) and N further drive transistors, where N is an arbitrary integer. 
     
     
       18. The method of  claim 17 , wherein N corresponds to a number of LPF cut-off frequencies at which the change in the voltage difference between the drive terminal of the pass device and the supply voltage of the linear regulator is compensated. 
     
     
       19. The method of  claim 12 , wherein: a. the first transistor comprises an NMOS transistor; b. the drive transistor comprises a PMOS transistor, the first terminal of the drive transistor comprising a source terminal of the PMOS transistor, the drive terminal of the drive transistor comprising a gate terminal of the PMOS transistor; c. the at least one further drive transistor comprises at least one further PMOS transistor, the first terminal of the at least one further drive transistor comprising a source terminal of the at least one further PMOS transistor, the drive terminal of the at least one further drive transistor comprising a gate terminal of the at least one further PMOS transistor; and d. the voltage difference between the drive terminal of the pass device and the supply voltage of the linear regulator is associated with a voltage difference between the gate and the source terminal of the PMOS transistor of the driver stage. 
     
     
       20. The method of  claim 12 , wherein the pass device comprises a PMOS transistor. 
     
     
       21. The method of  claim 12 , further comprising the steps of:
 a. providing a first amplifier stage; 
 b. providing a second amplifier stage coupled between the first amplifier stage and the driver stage; and 
 c. providing a capacitor coupled between the first amplifier stage and the output of the linear regulator. 
 
     
     
       22. The method of  claim 12 , wherein the driver stage comprises a buffer stage.