Memory cell sensing based on precharging an access line using a sense amplifier

Abstract

Methods, systems, and devices for operating a memory device are described. A sense amplifier may be used to precharge an access line to increase the reliability of the sensing operation. The access line may then charge share with the memory cell and a capacitor, which may be a reference capacitor, which may result in high-level states and low-level states on the access line. By precharging the access line with the sense amplifier and implementing charge sharing between the access line and a capacitor, the resulting high-level state and the low-level states on the access line may account for any offset voltage associated with the sense amplifier.

What is claimed is: 
     
       1. A method, comprising:
 precharging an access line to a first voltage, wherein the precharging comprises coupling the access line with a sense amplifier; 
 transferring charge between the access line and a memory cell after the precharging, wherein the access line transitions to a second voltage based at least in part on transferring the charge between the access line and the memory cell; 
 transferring charge between the access line and a capacitor after the precharging, wherein the access line transitions to a third voltage based at least in part on transferring the charge between the access line and the capacitor; and 
 determining a state of the memory cell based at least in part on amplifying the third voltage using the sense amplifier. 
 
     
     
       2. The method of  claim 1 , wherein precharging the access line to the first voltage comprises:
 coupling the access line with an input of the sense amplifier. 
 
     
     
       3. The method of  claim 2 , wherein precharging the access line to the first voltage further comprises:
 coupling the input of the sense amplifier with an output of the sense amplifier. 
 
     
     
       4. The method of  claim 3 , wherein precharging the access line to the first voltage further comprises:
 setting a second input of the sense amplifier to a target voltage. 
 
     
     
       5. The method of  claim 4 , wherein the first voltage is based at least in part on the target voltage and an offset voltage of the sense amplifier. 
     
     
       6. The method of  claim 3 , wherein the first voltage is based at least in part on a gain of the sense amplifier. 
     
     
       7. The method of  claim 3 , further comprising:
 decoupling, before transferring the charge between the access line and the memory cell, the input of the sense amplifier from the output of the sense amplifier. 
 
     
     
       8. The method of  claim 2 , wherein precharging the access line to the first voltage further comprises:
 setting the access line to an initial voltage that is greater than the first voltage; and 
 discharging the access line through the sense amplifier. 
 
     
     
       9. The method of  claim 8 , wherein the first voltage is based at least in part on a threshold voltage of the sense amplifier. 
     
     
       10. The method of  claim 8 , wherein discharging the access line through the sense amplifier comprises:
 coupling an output of the sense amplifier to a voltage source having a voltage that is less than the first voltage, the method further comprising: decoupling, before transferring the charge between the access line and the memory cell, the output of the sense amplifier from the voltage source. 
 
     
     
       11. The method of  claim 1 , wherein transferring the charge between the access line and the memory is concurrent with transferring the charge between the access line and the capacitor. 
     
     
       12. The method of  claim 1 , wherein transferring the charge between the access line and the capacitor comprises:
 coupling the capacitor with a fourth voltage; wherein the charge stored by the capacitor is based at least in part on the fourth voltage. 
 
     
     
       13. The method of  claim 12 , wherein the fourth voltage comprises a ground reference. 
     
     
       14. The method of  claim 1 , wherein:
 the third voltage has a first value when the state of the memory cell comprises a first state; 
 the third voltage has a second value when the state of the memory cell comprises second state; and 
 the first value is greater than and the second value is less than a center voltage, the center voltage based at least in part on an offset voltage of the sense amplifier. 
 
     
     
       15. The method of  claim 1 , further comprising:
 coupling, concurrent with at least one of transferring the charge between the access line and the memory cell or transferring the charge between the access line and the capacitor, an output of the sense amplifier with a voltage source. 
 
     
     
       16. The method of  claim 1 , wherein the sense amplifier comprises a differential amplifier. 
     
     
       17. The method of  claim 1 , wherein the sense amplifier comprises a folded cascode amplifier. 
     
     
       18. An apparatus, comprising:
 a memory cell configured to charge share with an access line; 
 a sense amplifier having an output node and an input node that is configured to be selectively coupled with the access line; 
 a capacitor configured to charge share with the access line; 
 a latch configured to latch a state of the memory cell based at least in part on a voltage at the output node of the sense amplifier; and 
 the sense amplifier comprises a single-ended amplifier configured to discharge the access line to a first voltage when the input node is coupled with the access line and the output node is coupled with a voltage source, and wherein the first voltage is based at least in part on a threshold voltage of a transistor included in the single-ended amplifier. 
 
     
     
       19. The apparatus of  claim 18 , wherein the sense amplifier comprises:
 a differential amplifier configured to drive the access line to the first voltage when the input node and the output node are coupled with the access line, and wherein the first voltage is based at least in part on a second voltage at a second input node of the differential amplifier. 
 
     
     
       20. The apparatus of  claim 19 , wherein coupling the input node and the output node with the access line forms a feedback loop. 
     
     
       21. The apparatus of  claim 18 , further comprising:
 a switching component configured to set the access line to an initial voltage that is greater than the first voltage. 
 
     
     
       22. The apparatus of  claim 18 , further comprising:
 a switching component configured to selectively couple the capacitor with the voltage source, wherein a direction of charge transfer between the capacitor and the access line is based at least in part on the voltage source. 
 
     
     
       23. An apparatus, comprising:
 a memory cell configured to charge share with an access line; 
 a sense amplifier having an output node and an input node that is configured to be selectively coupled with the access line; 
 a capacitor configured to charge share with the access line; 
 a latch configured to latch a state of the memory cell based at least in part on a voltage at the output node of the sense amplifier; 
 the output node is configured to be coupled with the access line at a first time and to be decoupled from the access line at a second time that is after the first time; 
 the memory cell is configured to be coupled with the access line at a third time that is after the second time; 
 the capacitor is configured to charge share with the access line at a fourth time that is after the second time; and 
 the latch is configured to latch the state of the memory cell at a fifth time that is after the fourth time. 
 
     
     
       24. An apparatus, comprising:
 a memory cell; 
 a sense amplifier; 
 a capacitor; and 
 a memory controller operable to: 
 precharge an access line to a first voltage based at least in part on coupling the access line with an input node of the sense amplifier; 
 cause the memory cell to charge share with the access line after precharging the access line, wherein the access line transitions to a second voltage based at least in part on exchanging charge with the memory cell; 
 cause the access line to charge share with the capacitor after precharging the access line, wherein the access line transitions to a third voltage based at least in part on exchanging charge with the capacitor; and 
 determine a state of the memory cell based at least in part on amplifying the third voltage using the sense amplifier.