Static random access memory cell structure

Abstract

A static random access memory (SRAM) cell structure includes a first inverter. The first inverter includes a first transistor and a second transistor. The first transistor includes a first source electrode and a first drain electrode. The first source electrode is connected to a first voltage source. The first source electrode includes a first doped region and a second doped region disposed in the first doped region, and a conductivity type of the second doped region is complementary to a conductivity type of the first doped region. The first drain electrode is connected to a first storage node. The second transistor includes a second source electrode and a second drain electrode. The second source electrode is connected to a second voltage source. The second drain electrode is connected to the first storage node.

What is claimed is: 
     
       1. A static random access memory (SRAM) cell structure, comprising:
 a first inverter, comprising:
 a first transistor, comprising:
 a first source electrode connected to a first voltage source, wherein the first source electrode comprises a first doped region and a second doped region disposed in the first doped region, and a conductivity type of the second doped region is complementary to a conductivity type of the first doped region; and 
 a first drain electrode connected to a first storage node; and 
 
 a second transistor, comprising:
 a second source electrode connected to a second voltage source; and 
 a second drain electrode connected to the first storage node. 
 
 
 
     
     
       2. The SRAM cell structure according to  claim 1 , further comprising:
 a first conductive layer disposed on the first doped region and the second doped region, wherein the first conductive layer is electrically connected with the first doped region and the second doped region. 
 
     
     
       3. The SRAM cell structure according to  claim 1 , wherein the first transistor further comprises:
 a first gate electrode; and 
 a first body region disposed under the first gate electrode and disposed between the first source electrode and the first drain electrode, wherein a part of the first doped region is disposed between the first body region and the second doped region. 
 
     
     
       4. The SRAM cell structure according to  claim 3 , further comprising:
 a first back side conductive layer disposed on the first body region, the first doped region, and the second doped region, wherein the first back side conductive layer is electrically connected with the first body region, the first doped region, and the second doped region. 
 
     
     
       5. The SRAM cell structure according to  claim 1 , wherein the second source electrode comprises a third doped region and a fourth doped region disposed in the third doped region, and a conductivity type of the fourth doped region is complementary to a conductivity type of the third doped region. 
     
     
       6. The SRAM cell structure according to  claim 5 , wherein the conductivity type of the first doped region is identical to the conductivity type of the fourth doped region, and the conductivity type of the second doped region is identical to the conductivity type of the third doped region. 
     
     
       7. The SRAM cell structure according to  claim 5 , further comprising:
 a second conductive layer disposed on the third doped region and the fourth doped region, wherein the second conductive layer is electrically connected with the third doped region and the fourth doped region. 
 
     
     
       8. The SRAM cell structure according to  claim 5 , wherein the second transistor further comprises:
 a second gate electrode; and 
 a second body region disposed under the second gate electrode and disposed between the second source electrode and the second drain electrode, wherein a part of the third doped region is disposed between the second body region and the fourth doped region. 
 
     
     
       9. The SRAM cell structure according to  claim 8 , further comprising:
 a second back side conductive layer disposed on the second body region, the third doped region, and the fourth doped region, wherein the second back side conductive layer is electrically connected with the second body region, the third doped region, and the fourth doped region. 
 
     
     
       10. The SRAM cell structure according to  claim 1 , wherein the first voltage source is ground voltage, the second voltage source is supply voltage, the first transistor is a pull-down transistor, and the second transistor is a pull-up transistor. 
     
     
       11. The SRAM cell structure according to  claim 1 , wherein the first voltage source is supply voltage, the second voltage source is ground voltage, the first transistor is a pull-up transistor, and the second transistor is a pull-down transistor. 
     
     
       12. The SRAM cell structure according to  claim 1 , further comprising:
 a second inverter, comprising:
 a third transistor, comprising:
 a third source electrode connected to the first voltage source, wherein the third source electrode comprises a fifth doped region and a sixth doped region disposed in the fifth doped region, and a conductivity type of the sixth doped region is complementary to a conductivity type of the fifth doped region; and 
 a third drain electrode connected to a second storage node; and 
 
 a fourth transistor, comprising:
 a fourth source electrode connected to the second voltage source; and 
 a fourth drain electrode connected to the second storage node. 
 
 
 
     
     
       13. The SRAM cell structure according to  claim 12 , wherein the fourth source electrode comprises a seventh doped region and an eighth doped region disposed in the seventh doped region, and a conductivity type of the eighth doped region is complementary to a conductivity type of the seventh doped region. 
     
     
       14. A static random access memory (SRAM) cell structure, comprising:
 a first inverter, comprising:
 a first transistor, comprising:
 a first source electrode connected to a first voltage source, wherein the first source electrode comprises a first doped region and a second doped region disposed in the first doped region, and a conductivity type of the second doped region is complementary to a conductivity type of the first doped region, wherein the second doped region divides the first doped region into two separated parts disposed at two opposite sides of the second doped region respectively; and 
 a first drain electrode connected to a first storage node; and 
 
 a second transistor, comprising:
 a second source electrode connected to a second voltage source; and 
 a second drain electrode connected to the first storage node. 
 
 
 
     
     
       15. The SRAM cell structure according to  claim 14 , further comprising:
 a first conductive layer disposed on the first doped region and the second doped region, wherein the first conductive layer is electrically connected with the first doped region and the second doped region. 
 
     
     
       16. The SRAM cell structure according to  claim 14 , wherein the second source electrode comprises a third doped region and a fourth doped region disposed in the third doped region, and a conductivity type of the fourth doped region is complementary to a conductivity type of the third doped region. 
     
     
       17. The SRAM cell structure according to  claim 16 , wherein the conductivity type of the first doped region is identical to the conductivity type of the fourth doped region, and the conductivity type of the second doped region is identical to the conductivity type of the third doped region. 
     
     
       18. The SRAM cell structure according to  claim 16 , further comprising:
 a second conductive layer disposed on the third doped region and the fourth doped region, wherein the second conductive layer is electrically connected with the third doped region and the fourth doped region. 
 
     
     
       19. The SRAM cell structure according to  claim 16 , wherein the fourth doped region divides the third doped region into two separated parts disposed at two opposite sides of the fourth doped region respectively. 
     
     
       20. The SRAM cell structure according to  claim 14 , further comprising:
 a second inverter, comprising:
 a third transistor, comprising:
 a third source electrode connected to the first voltage source, wherein the third source electrode comprises a fifth doped region and a sixth doped region disposed in the fifth doped region, and a conductivity type of the sixth doped region is complementary to a conductivity type of the fifth doped region; and 
 a third drain electrode connected to a second storage node; and 
 
 a fourth transistor, comprising:
 a fourth source electrode connected to the second voltage source, wherein the fourth source electrode comprises a seventh doped region and an eighth doped region disposed in the seventh doped region, and a conductivity type of the eighth doped region is complementary to a conductivity type of the seventh doped region; and 
 a fourth drain electrode connected to the second storage node.