Limited pin test interface with analog test bus

Abstract

Certain aspects of the disclosure are directed toward test control and test access configuration via two pins on an integrated circuit (IC). According to a specific example, an IC chip-based apparatus is used in connection with a controller for testing a target IC. The IC chip-based apparatus includes an event (capture) circuit configured and arranged to control logic states through which a static test configuration is selected for a given event detected in response to a clock signal and to a data signal respectively derived from the controller. A test-operation control circuit may be configured and arranged to test the target IC by selectively configuring each of the clock pin and the I/O pin of the controller for use as an analog test bus, data input to the controller or data output from the controller, and carrying out dynamic operations by communicating test signals via pins of the target IC.

What is claimed is: 
     
       1. For use in connection with a controller in testing a target integrated circuit (IC), an IC chip-based apparatus comprising:
 an event capture circuit configured and arranged to control logic states through which a static test configuration is selected for a given event detected in response to a clock signal and to a data signal respectively derived from the controller; 
 a test-operation control circuit configured and arranged to test the target IC by:
 selectively configuring each of clock pin and a I/O pin of the controller for use as an analog test bus, data input to the controller or data output from the controller; and 
 carrying out dynamic operations by communicating test signals via pins of the target IC which are:
 compliant with selected test configuration; 
 in synchronism with the clock signal of the controller; and 
 in accordance with a test protocol as selected in response to the selected test configuration. 
 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the IC chip-based apparatus is configured and arranged as a two-pin test interface device configured and arranged with two pins to provide two respective connections with the clock pin and the I/O pin of the controller that are selectively configurable as the analog test bus, data input to the controller or data output from the controller, and to provide a plurality of target-IC connections with pins of the target IC. 
     
     
       3. The apparatus of  claim 1 , wherein the IC chip-based apparatus is configured and arranged as a two-pin test interface device configured and arranged with two pins to provide two respective connections with the clock pin and the I/O pin of the controller that are selectively configurable as the analog test bus, data input to the controller or data output from the controller, and to provide a plurality of target-IC connections with TDO, TDI and TCK pins of the target IC for communicating scan test signals. 
     
     
       4. The apparatus of  claim 1 , wherein the IC chip-based apparatus is configured and arranged as a two-pin test interface device configured and arranged with two pins to provide two respective connections with the clock pin and the I/O pin of the controller that are selectively configurable as the analog test bus, data input to the controller or data output from the controller, and to provide a plurality of target-IC connections of the target IC for communicating test signals operating at a fractional frequency rate relative to the clock signal of the controller. 
     
     
       5. The apparatus of  claim 1 , wherein the IC chip-based apparatus is configured and arranged as a two-pin test interface device configured and arranged with two pins to provide two respective connections with the clock pin and the I/O pin of the controller, wherein the I/O pin is selectively configured, during operation of the test-operation control circuit, for use as at least one of digital data input and digital data output. 
     
     
       6. The apparatus of  claim 1 , wherein the IC chip-based apparatus is configured and arranged as a two-pin test interface device configured and arranged with two pins to provide two respective connections with the clock pin and the I/O pin of the controller, wherein the I/O pin is selectively configured for use as digital data input during operations in which the event capture circuit transitions through event sequences in response to the test-operation control circuit. 
     
     
       7. The apparatus of  claim 1 , wherein the event capture circuit and the test-operation control circuit are configured and arranged to enter into a locked logic state, corresponding with a mode for testing the target IC, and further configured and arranged to unlock from the locked logic state in response to a reset signal or power-down mode. 
     
     
       8. The apparatus of  claim 1 , further including an event counter circuit configured and arranged, in response to the clock signal and to the data signal by counting or tracking through a sequence of signal-indicated events provided by the controller, to provide signals as used by the event capture circuit for controlling the logic states. 
     
     
       9. The apparatus of  claim 1 , further including an interface-signal direction control circuit configured and arranged, in response to a control signal provided from the target IC, to control whether the I/O pin of the controller is to be used by circuitry, including the event capture circuit, for providing data as data input to the controller or providing data as data output from the controller. 
     
     
       10. The apparatus of  claim 1 , further including the controller including circuitry configured and arranged with the clock pin and the I/O pin and with circuitry configured to perform testing. 
     
     
       11. The IC chip-based apparatus of  claim 1 , further including an interface-signal direction control circuit configured and arranged, in response to a control signal provided from the target IC, to control whether the I/O pin of the controller is to be used by circuitry, including the event capture circuit, for providing data as data input to the controller or providing data as data output from the controller and wherein the IC chip-based apparatus is configured and arranged as a two-pin test interface device configured and arranged with two pins to provide two respective connections with the clock pin and the I/O pin of the controller, wherein the I/O pin is selectively configured for use as digital data input during operations in which the event capture circuit transitions through event sequences in response to the test-operation control circuit, wherein the event capture circuit and the test-operation control circuit are configured and arranged to enter into a locked logic state, corresponding with a mode for testing the target IC, and further configured and arranged to unlock from the locked logic state in response to a reset signal or power-down mode. 
     
     
       12. The apparatus of  claim 1 , wherein the IC chip-based apparatus is configured and arranged as a two-pin test interface device configured and arranged with two pins to provide two respective connections with the clock pin and the I/O pin of the controller that are selectively configurable as the data input to the controller or data output from the controller, and to provide a plurality of target-IC connections with pins of the target IC. 
     
     
       13. The apparatus of  claim 1 , wherein the test-operation control circuit is configured and arranged to test the target IC by sending a test mode select (TMS) signal to a test access port (TAP) controller. 
     
     
       14. For use in connection with a controller in testing a target integrated circuit (IC), a method comprising:
 controlling logic states in an event capture circuit by controlling logic states, within the event capture circuit, to set and enable a static test configuration for a given event detected in response to a clock signal and to a data signal respectively derived from a clock pin and an I/O pin of the controller; 
 using a test-operation control circuit in response to the event capture circuit, testing the target IC by:
 selectively configuring the clock pin and the I/O pin of the controller for use as an analog test bus, data input to the controller or data output from the controller; and 
 carrying out dynamic operations by communicating test signals via pins of the target IC which are:
 compliant with the enabled test configuration; 
 in synchronism with the clock signal of the controller; and 
 in accordance with a test protocol as selected in response to the selected test configuration. 
 
 
 
     
     
       15. The method of  claim 14 , wherein the event capture circuit and the test-operation control circuit are configured as a two-pin test interface circuit configured and arranged with two pins to provide two respective connections with the clock pin and the I/O pin of the controller that are selectively configurable as the analog test bus, data input to the controller or data output from the controller, and to provide a plurality of target-IC connections with pins of the target IC. 
     
     
       16. The method of  claim 14 , wherein the event capture circuit and the test-operation control circuit are configured as a two-pin test interface circuit configured and arranged with two pins to provide two respective connections with the clock pin and the I/O pin of the controller, wherein the clock pin and the I/O pin of the controller that are selectively configurable for use as an analog test bus, data input to the controller or data output from the controller, and to provide a plurality of target-IC connections with TDO, TDI and TCK pins of the target IC for communicating scan test signals. 
     
     
       17. The method of  claim 14 , wherein the I/O pin is selectively configured, during operation of the test-operation control circuit, for use as either a digital data input or a digital data output. 
     
     
       18. The method of  claim 14 , wherein the event capture circuit is integrated with an event counter circuit which operates in response to the clock signal and to the data signal by counting or tracking through a sequence of signal-indicated events provided by the controller, to provide signals as used by the event capture circuit for controlling the logic states. 
     
     
       19. The method of  claim 14 , wherein the event capture circuit and the test-operation control circuit respond to certain signals from the controller by entering into a locked logic state, corresponding with a mode for testing the target IC, and wherein the locked logic state is unlocked in response to a reset signal or power-down mode.