Chip and power planning method

Abstract

A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.

What is claimed is: 
     
       1. A power planning method, comprising:
 (a) providing a chip with a plurality of macros placed thereon; 
 (b) dividing a placement region of the chip into a plurality of sub-regions according to locations of the macros; 
 (c) determining, for each sub-region, a total power routing width (TPRW) of vertical power stripes (VPSs); 
 (d) determining a number of the VPSs for each said region by dividing the TPRW with an effective stripe width; and 
 (e) determining locations of the VPSs for each said sub-region; 
 wherein the step (b) comprises: 
 determining, for each said macro, a first horizontal line overlapping a horizontal power stripe (HPS) nearest a top edge of the macro and being extended until bumping into another macro or a boundary of the placement region; 
 determining, for each said macro, a second horizontal line overlapping a HPS nearest a bottom edge of the macro and being extended until bumping into another macro or the boundary of the placement region; 
 determining, for each said macro, a first vertical line overlapping a left edge of the macro and being extended until bumping into another macro or the boundary of the placement region; and 
 determining, for each said macro, a second vertical line overlapping a right edge of the macro and being extended until bumping into another macro or the boundary of the placement region; 
 wherein the first horizontal lines, the second horizontal lines, the first vertical lines and the second vertical lines of the plurality of macros therefore divide the placement region into the plurality of sub-regions. 
 
     
     
       2. The method of  claim 1 , wherein the horizontal power stripes (HPSs) are disposed in a first top metal layer, and the VPSs are disposed in a second top metal layer below the HPSs. 
     
     
       3. The method of  claim 1 , further comprising:
 merging at least one sub-region with a neighboring sub-region or sub-regions before the step (c). 
 
     
     
       4. The method of  claim 3 , wherein if the sub-region contains less than a predetermined number of HPSs, the sub-region is then merged with a lower sub-region if it exists and the two sub-regions have a same width, otherwise, the sub-region is then merged with a higher sub-region if it exists and the two sub-regions have a same width. 
     
     
       5. The method of  claim 3 , wherein if the sub-region contains less than a predetermined number of the VPSs, the sub-region is then merged with a left sub-region if it exists and the two sub-regions have a same height, otherwise, the sub-region is then merged with a right sub-region if it exists and the two sub-regions have a same height. 
     
     
       6. The method of  claim 1 , wherein in the step (c), the total power routing width (TPRW) is determined such that voltage-drop and electromigration constraints are satisfied with a minimal routing area. 
     
     
       7. The method of  claim 1 , wherein the VPSs are non-uniformly disposed such that distances between adjacent VPSs in the sub-region are not necessary the same. 
     
     
       8. The method of  claim 1 , wherein at least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.