Timing-drift calibration

Abstract

The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

What is claimed is: 
     
       1. A dynamic random access memory (DRAM) chip having a memory core, the memory core including a plurality of storage cells, the DRAM chip comprising:
 a signaling interface to receive an instruction from a memory controller that is separate from the DRAM chip; 
 an oscillator circuit to generate an oscillating signal; and 
 a counter circuit coupled to the oscillator circuit, wherein, in response to the instruction, the counter circuit is to begin a count of a number of edges of the oscillating signal, and wherein the counter circuit is to count the number of edges of the oscillating signal during a measurement duration period. 
 
     
     
       2. The DRAM chip of  claim 1 , wherein the number of edges counted during the measurement duration period is representative of a frequency measurement of the oscillating signal. 
     
     
       3. The DRAM chip of  claim 1 , further comprising:
 a circuit to receive a clock signal, wherein the instruction received from the memory controller specifies the measurement duration period, and wherein the counter circuit is to count the number of edges of the oscillating signal using the clock signal to control the measurement duration period. 
 
     
     
       4. The DRAM chip of  claim 3 , wherein the measurement duration period is specified by a value provided by the instruction, the DRAM further comprising:
 a logic circuit coupled to the counter circuit, the logic circuit to terminate the measurement duration period in response to a number of edges of the clock signal reaching the value. 
 
     
     
       5. The DRAM chip of  claim 1 , further comprising:
 a clock distribution circuit having a first timing delay, wherein a buffer chain in the oscillator circuit comprises a replica of a clock path in the clock distribution circuit, the oscillator circuit having a second timing delay. 
 
     
     
       6. The DRAM chip of  claim 1 , further comprising:
 a logic circuit coupled to the counter circuit, the logic circuit to reset the counter in response to the instruction prior to beginning the count. 
 
     
     
       7. The DRAM chip of  claim 1 , wherein the signaling interface is further to receive an instruction from the memory controller to output the count to the memory controller. 
     
     
       8. The DRAM chip of  claim 1 , further comprising:
 one or more control registers, the instruction to trigger writing a control value to one of the one or more registers, wherein the counter circuit is to begin the count in response to the control value. 
 
     
     
       9. A method of operation in a dynamic random access memory (DRAM) chip having a memory core, the memory core including a plurality of storage cells, the method comprising:
 receiving an instruction from a memory controller that is separate from the DRAM chip; and 
 in response to the instruction:
 generating an oscillating signal; and 
 commencing a count of a number of edges of the oscillating signal, wherein the count of the number of edges of the oscillating signal occurs during a measurement duration period. 
 
 
     
     
       10. The method of  claim 9 , wherein the number of edges counted during the measurement duration period is representative of a frequency measurement of the oscillating signal. 
     
     
       11. The method of  claim 9 , wherein the instruction received from the memory controller specifies the measurement duration period, the method further comprising:
 receiving a clock signal; and 
 counting the number of edges of the oscillating signal using the clock signal to control the measurement duration period. 
 
     
     
       12. The method of  claim 11 , wherein the measurement duration period is specified by a value provided by the instruction, the method further comprising:
 terminating the measurement duration period in response to a number of edges of the clock signal reaching value. 
 
     
     
       13. The method of  claim 9 , further comprising:
 resetting a counter in response to the instruction prior to beginning the count.