P
US10600839B2ActiveUtilityPatentIndex 94

Semiconductor device including oxide semiconductor

Assignee: SEMICONDUCTOR ENERGY LABPriority: Dec 10, 2014Filed: Sep 5, 2018Granted: Mar 24, 2020
Est. expiryDec 10, 2034(~8.4 yrs left)· nominal 20-yr term from priority
Inventors:KUROKAWA YOSHIYUKI
H01L 27/14609H01L 31/0322H01L 27/14643H01L 27/14636H01L 31/0272H01L 27/14667H01L 27/14612H01L 29/24H01L 27/14623H10D 62/80H10F 77/126H10F 77/121H10F 39/8057H10F 39/8037H10F 39/811H10F 39/803H10F 39/192H10F 39/18Y02P70/50Y02E10/541
94
PatentIndex Score
16
Cited by
238
References
6
Claims

Abstract

A semiconductor device including pixels arranged in a matrix of n rows and m columns, in which the pixels in the m-th column are shielded from light, is provided.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A semiconductor device comprising:
 memory elements arranged in a matrix of n rows and m columns, where each of n and m is a natural number of 2 or more, 
 wherein each of the memory elements comprise a transistor whose channel formation region comprises an oxide semiconductor, and 
 wherein the semiconductor device performs vector matrix multiplication while canceling an effect due to dark current of the memory elements. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein the memory elements are configured to output pulse, depending on a threshold, so that the semiconductor device performs vector matrix multiplication. 
     
     
       3. A semiconductor device comprising:
 memory elements arranged in a matrix of n rows and m columns, where each of n and m is a natural number of 2 or more; and 
 reference memory elements that are shielded from light, 
 wherein each of the memory elements comprise a transistor whose channel formation region comprises an oxide semiconductor, and 
 wherein the semiconductor device performs vector matrix multiplication while subtracting dark current of the reference memory elements. 
 
     
     
       4. The semiconductor device according to  claim 3 , wherein the memory elements are configured to output pulse, depending on a threshold, so that the semiconductor device performs vector matrix multiplication. 
     
     
       5. A semiconductor device comprising:
 memory elements arranged in a matrix of n rows and m columns, where each of n and m is a natural number of 2 or more, 
 wherein each of the memory elements comprise a transistor whose channel formation region comprises an oxide semiconductor, 
 wherein the semiconductor device performs vector matrix multiplication while canceling an effect due to dark current of the memory elements, and 
 wherein the semiconductor device performs smoothing processing, edge enhancement processing, or cosine transform by the vector matrix multiplication. 
 
     
     
       6. The semiconductor device according to  claim 5 , wherein the memory elements are configured to output pulse, depending on a threshold, so that the semiconductor device performs vector matrix multiplication.

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