Memory device with programming cycle stages

Abstract

A memory device comprising: a memory cell array and a memory controller configured to program data to memory cells during a programming cycle using operations comprising: during a setup stage, providing a first voltage level to word lines, a second voltage level to a first dummy word line, and a fourth voltage level to second dummy word lines being different from the first dummy word line, wherein the first voltage level is lower than a threshold voltage of a first transistor coupled to the first dummy word line and the second voltage level and the fourth voltage are higher than the threshold voltage, during a program stage, providing a third voltage level to first word lines to program data to memory cells coupled to the first word lines, the second voltage level to the first dummy word line, and the fourth voltage level to the second dummy word lines.

What is claimed is: 
     
       1. A memory device comprising:
 a memory controller; and 
 a memory cell array that includes one or more memory blocks, wherein each memory block of the one or more memory blocks includes one or more strings, each string of the one or more strings comprising:
 a plurality of dummy word lines, 
 a plurality of word lines, and 
 a plurality of memory cells respectively coupled to the plurality of word lines, 
 wherein the memory controller programs one or more data to one or more memory cells of the plurality of memory cells using operations during a programming cycle, the operations comprising: 
 
 during a setup stage of the programming cycle,
 providing a first voltage level to the plurality of word lines, 
 providing a second voltage level to a first dummy word line of the plurality of dummy word lines, and 
 providing a fourth voltage level to second dummy word lines of the plurality of dummy word lines, the second dummy word lines being different from the first dummy word line, 
 wherein (i) the first voltage level is lower than a threshold voltage of a first transistor coupled to the first dummy word line and (ii) the second voltage level and the fourth voltage are higher than the threshold voltage of the first transistor, 
 
 during a program stage of the programming cycle,
 providing a third voltage level to one or more first word lines of the plurality of word lines to program one or more data to one or more memory cells coupled to the one or more first word lines, 
 providing the second voltage level to the first dummy word line of the plurality of dummy word lines, and 
 providing the fourth voltage level to the second dummy word lines of the plurality of dummy word lines. 
 
 
     
     
       2. The memory device of  claim 1 , wherein the operations further comprises:
 during the program stage of the programming cycle,
 providing a fifth voltage level to one or more second word lines of the plurality of word lines to maintain one or more data stored in one or more memory cells coupled to the one or more second word lines. 
 
 
     
     
       3. The memory device of  claim 1 , wherein the first dummy word line is a dummy word line from the plurality of dummy word lines that is closest to the plurality of word lines. 
     
     
       4. The memory device of  claim 1 , wherein the setup stage of the programming cycle continues for 1-10 μs. 
     
     
       5. The memory device of  claim 1 , wherein the program stage of the programming cycle continues for 10-100 μs. 
     
     
       6. The memory device of  claim 2 , wherein the third voltage level is between 13 and 25V and the fifth voltage level is between 6 and 10V. 
     
     
       7. The memory device of  claim 1 , wherein the second voltage level is between 6 and 10V. 
     
     
       8. The memory device of  claim 2 , wherein the second voltage level is the same as the fifth voltage level. 
     
     
       9. The memory device of  claim 2 , wherein the second voltage level is different from the fifth voltage level that is higher than the threshold voltage. 
     
     
       10. A method for programming, during a programming cycle, one or more data to a memory cell array that includes one or more memory blocks, wherein each memory block of the one or more memory blocks includes one or more strings, each string of the one or more strings comprising:
 a plurality of dummy word lines, 
 a plurality of word lines, and 
 a plurality of memory cells respectively coupled to the plurality of word lines, 
 wherein the method comprises: 
 during a setup stage of the programming cycle,
 providing a first voltage level to the plurality of word lines, 
 providing a second voltage level to a first dummy word line of the plurality of dummy word lines, and 
 providing a fourth voltage level to second dummy word lines of the plurality of dummy word lines, the second dummy word lines being different from the first dummy word line, 
 wherein (i) the first voltage level is lower than a threshold voltage of a first transistor coupled to the first dummy word line and (ii) the second voltage level and the fourth voltage level are higher than the threshold voltage of the first transistor, 
 
 during a program stage of the programming cycle,
 providing a third voltage level to one or more first word lines of the plurality of word lines to program one or more data to one or more memory cells coupled to the one or more first word lines, 
 providing the second voltage level to the first dummy word line of the plurality of dummy word lines, and 
 providing the fourth voltage level to the second dummy word lines. 
 
 
     
     
       11. The method of  claim 10 , further comprising:
 during the program stage of the programming cycle,
 providing a fifth voltage level to one or more second word lines of the plurality of word lines to maintain one or more data stored in one or more memory cells coupled to the one or more second word lines. 
 
 
     
     
       12. The method of  claim 10 , wherein the first dummy word line is a dummy word line from the plurality of dummy word lines that is closest to the plurality of word lines. 
     
     
       13. The method of  claim 10 , wherein the setup stage of the programming cycle continues for 1-10 μs. 
     
     
       14. The method of  claim 10 , wherein the program stage of the programming cycle continues for 10-100 μs. 
     
     
       15. The method of  claim 11 , wherein the third voltage level is between 13 and 25V and the fifth voltage level is between 6 and 10V. 
     
     
       16. The method of  claim 10 , wherein the second voltage level is between 6 and 10V. 
     
     
       17. The method of  claim 11 , wherein the second voltage level is the same as the fifth voltage level. 
     
     
       18. The method of  claim 11 , wherein the second voltage level is different from the fifth voltage level that is higher than the threshold voltage. 
     
     
       19. A memory device comprising:
 a memory controller; and 
 a memory cell array that includes one or more memory blocks, wherein each memory block of the one or more memory blocks includes one or more strings, each string of the one or more strings comprising:
 a plurality of dummy word lines, 
 a plurality of word lines, and 
 a plurality of memory cells respectively coupled to the plurality of word lines, 
 wherein the memory controller is configured to program one or more data to one or more memory cells of the plurality of memory cells using operations during a programming cycle, the operations comprising: 
 
 during a setup stage of the programming cycle,
 providing a first voltage level to the plurality of word lines, 
 providing a second voltage level to a first dummy word line of the plurality of dummy word lines, and 
 providing a fourth voltage level to second dummy word lines of the plurality of dummy word lines, the second dummy word lines being different from the first dummy word line, 
 wherein (i) the first voltage level is lower than a threshold voltage of a first transistor coupled to the first dummy word line and (ii) the second voltage level and the fourth voltage level are higher than the threshold voltage of the first transistor, 
 
 during a program stage of the programming cycle,
 providing a third voltage level to one or more first word lines of the plurality of word lines to program one or more data to one or more memory cells coupled to the one or more first word lines, and 
 providing a fifth voltage level to the first dummy word line of the plurality of dummy word lines, and 
 providing the fourth voltage level to the second dummy word lines, 
 wherein the fifth voltage level is higher than the second voltage level. 
 
 
     
     
       20. The memory device of  claim 19 , wherein the first dummy word line is a dummy word line from the plurality of dummy word lines that is closest to the plurality of word lines.