Voltage regulator

Abstract

A voltage regulator is arranged to receive an input voltage (V in ) and produce a regulated output voltage (V out ) and comprises: a current source transistor (M source ) and a current sink transistor (M sink ) arranged to provide the output voltage at a node therebetween; a first error amplifier; and a second error amplifier. The first error amplifier is arranged to apply a first control voltage to the gate terminal of the current source transistor, wherein the first control voltage is dependent on the difference between the feedback voltage (V fb ) and the reference voltage (V ref ). The second error amplifier arranged in parallel to the first error amplifier, the second error amplifier being arranged to apply a second control voltage to the gate terminal of the current sink transistor, wherein the second control voltage is dependent on the difference between the feedback voltage and the reference voltage. The feedback voltage is derived from the output voltage.

The invention claimed is: 
     
       1. A voltage regulator arranged to receive an input voltage and produce a regulated output voltage, the voltage regulator comprising:
 a current source transistor and a current sink transistor arranged to provide the output voltage at a node therebetween; 
 a first error amplifier arranged to compare a feedback voltage to a reference voltage and apply a first control voltage to a gate terminal of the current source transistor, wherein said first control voltage is dependent on a difference between the feedback voltage and the reference voltage; 
 a second error amplifier arranged in parallel to the first error amplifier, said second error amplifier being arranged to compare the feedback voltage to the reference voltage and apply a second control voltage to a gate terminal of the current sink transistor, wherein said second control voltage is dependent on a difference between the feedback voltage and the reference voltage; 
 wherein said feedback voltage is derived from the output voltage and wherein the first error amplifier is arranged to vary a bias current provided to the second error amplifier. 
 
     
     
       2. The voltage regulator as claimed in  claim 1 , comprising a feedback network arranged to provide the feedback voltage which depends on the output voltage. 
     
     
       3. The voltage regulator as claimed in  claim 2 , wherein the feedback network comprises a ladder of diode-connected metal-oxide-semiconductor field-effect-transistors. 
     
     
       4. The voltage regulator as claimed in  claim 1 , wherein the current source transistor comprises a p-channel metal-oxide-semiconductor field-effect-transistor. 
     
     
       5. The voltage regulator as claimed in  claim 1 , wherein the current sink transistor comprises an n-channel metal-oxide-semiconductor field-effect-transistor. 
     
     
       6. The voltage regulator as claimed in  claim 1 , wherein the source terminal of the current source transistor is connected to the input voltage. 
     
     
       7. The voltage regulator as claimed in  claim 1 , wherein the source terminal of the current sink transistor is connected to ground. 
     
     
       8. The voltage regulator as claimed in  claim 1 , wherein the respective drain terminals of the current source transistor and the current sink transistor are connected together at the node arranged to provide the output voltage. 
     
     
       9. The voltage regulator as claimed in  claim 1 , wherein the first error amplifier comprises first and second differential n-channel metal-oxide-semiconductor field-effect-transistors, arranged such that the gate terminal of the first differential n-channel metal-oxide-semiconductor field-effect-transistor is connected to the feedback voltage, and the gate terminal of the second differential n-channel metal-oxide-semiconductor field-effect-transistor is connected to the reference voltage. 
     
     
       10. The voltage regulator as claimed in  claim 1 , wherein the first error amplifier comprises a constant current source. 
     
     
       11. The voltage regulator as claimed in  claim 9 , wherein the first error amplifier comprises a constant current source connected to the source terminals of said first and second differential n-channel metal-oxide-semiconductor field-effect-transistors. 
     
     
       12. The voltage regulator as claimed in  claim 9 , wherein the first error amplifier comprises a first current mirror comprising first and second mirror p-channel metal-oxide-semiconductor field-effect-transistors arranged such that:
 the gate and drain terminals of the first mirror p-channel metal-oxide-semiconductor field-effect-transistor are connected to the gate terminal of the second mirror p-channel metal-oxide-semiconductor field-effect-transistor and the drain terminal of the first differential n-channel metal-oxide-semiconductor field-effect-transistor; 
 the drain terminal of the second mirror p-channel metal-oxide-semiconductor field-effect-transistor is connected to the drain terminal of the second differential n-channel metal-oxide-semiconductor field-effect-transistor; and 
 the source terminals of the first and second mirror p-channel metal-oxide-semiconductor field-effect-transistors are connected to the input voltage. 
 
     
     
       13. The voltage regulator as claimed in  claim 12 , wherein the second error amplifier comprises a tail transistor arranged such that its drain terminal is connected to the respective source terminals of the first and second differential p-channel metal-oxide-semiconductor field-effect-transistors and its gate terminal is connected to the gate and drain terminals of the first mirror p-channel metal-oxide-semiconductor field-effect-transistor. 
     
     
       14. The voltage regulator as claimed in  claim 13 , wherein the tail transistor is a p-channel metal-oxide-semiconductor field-effect-transistor. 
     
     
       15. The voltage regulator as claimed in  claim 1 , wherein the second error amplifier comprises first and second differential p-channel metal-oxide-semiconductor field-effect-transistors, arranged such that the gate terminal of the first differential p-channel metal-oxide-semiconductor field-effect-transistor is connected to the feedback voltage, and the gate terminal of the second differential p-channel metal-oxide-semiconductor field-effect-transistor is connected to the reference voltage. 
     
     
       16. The voltage regulator as claimed in  claim 15 , wherein the second error amplifier further comprises a second current mirror comprising first and second mirror n-channel metal-oxide-semiconductor field-effect-transistors arranged such that:
 the gate and drain terminals of the first mirror n-channel metal-oxide-semiconductor field-effect-transistor are connected to the gate terminal of the second mirror n-channel metal-oxide-semiconductor field-effect-transistor and the drain terminal of the first differential p-channel metal-oxide-semiconductor field-effect-transistor; 
 the drain terminal of the second mirror n-channel metal-oxide-semiconductor field-effect-transistor is connected to the drain terminal of the second differential p-channel metal-oxide-semiconductor field-effect-transistor; and 
 the source terminals of the first and second mirror n-channel metal-oxide-semiconductor field-effect-transistors are connected to ground.