Semiconductor optical device and method of manufacturing the same
Abstract
Provided is a semiconductor optical device with light extraction efficiency or light collecting efficiency higher than that of conventional devices and with a reduced peeling ratio of a wiring electrode portion, and a method of manufacturing the same. In the semiconductor optical, a wiring electrode portion 120 is provided on a surface of a semiconductor layer 110 that serves as a light emitting surface or a light receiving surface, the line width W 1 of the wiring electrode portion 120 is 2 μm or more and 5 μm or less, the wiring electrode portion 120 has a metal layer 121 on the semiconductor layer 110 and a conductive hard film 122 on the metal layer 121 , and the conductive hard film 122 is harder than the metal layer 121.
Claims
exact text as granted — not AI-modifiedThe invention claimed is:
1. A semiconductor optical device comprising a semiconductor layer and a wiring electrode portion on a surface of the semiconductor layer that serves as one of a light emitting surface and a light receiving surface,
wherein a line width of the wiring electrode portion is 2 μm or more and 5 μm or less,
the wiring electrode portion has a metal layer on the semiconductor layer and a conductive hard film on the metal layer,
the conductive hard film is harder than the metal layer, and
a thickness of the conductive hard film is 0.7 μm or more and 1.5 μm or less.
2. The semiconductor optical device according to claim 1 , wherein a vacant space is present between a region under a peripheral portion of the wiring electrode portion and the semiconductor layer.
3. The semiconductor optical device according to claim 2 ,
wherein the surface of the semiconductor layer has a flat surface portion and a rough surface portion,
part of the surface of the semiconductor wafer at a joint center where the surface of the semiconductor layer and the wiring electrode portion are joined to each other is the flat surface portion, and
the vacant space is constituted by the rough surface portion.
4. The semiconductor optical device according to claim 3 , wherein a line width of the flat surface portion at the joint center is 1.0 μm or more.
5. The semiconductor optical device according to claim 3 , wherein at the joint center, a line width of the flat surface portion is smaller than a line width of the wiring electrode portion by 0.5 μm or more.
6. The semiconductor optical device according to claim 1 , wherein the conductive hard film is a nitride of one or more metal elements selected from the group consisting of Ti, Ta, Cr, W, Mo, and V.
7. The semiconductor optical device according to claim 1 , wherein the semiconductor layer includes an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer in this order, and the surface of the semiconductor layer is a surface of one of the n-type semiconductor layer and the p-type semiconductor layer.
8. A method of manufacturing a semiconductor optical device, comprising a wiring electrode portion formation step of forming a wiring electrode portion on a surface of a semiconductor layer that serves as one of a light emitting surface and a light receiving surface,
wherein a line width of the wiring electrode portion is 2 μm or more and 5 μm or less, and
the wiring electrode portion formation step includes a first step of forming a metal layer on the surface of the semiconductor layer and a second step of forming a conductive hard film having a thickness of 0.7 μm or more and 1.5 μm or less on the metal layer.
9. The method of manufacturing a semiconductor optical device, according to claim 8 , further comprising a vacant space formation step of forming a vacant space between a region under a peripheral portion of the wiring electrode portion and the semiconductor layer after the wiring electrode formation step.
10. The method of manufacturing a semiconductor optical device, according to claim 9 , wherein in the vacant space formation step, the surface of the semiconductor layer is wet etched to roughen a part of the surface of the semiconductor layer lying under a peripheral portion of the wiring electrode portion to form the vacant-space.Cited by (0)
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