Semiconductor device with patterned ground shielding

Abstract

Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a glue oxide layer; 
 a first dielectric layer underlying the glue oxide layer; 
 a first inductor underlying the first dielectric layer; 
 a second dielectric layer underlying the first inductor; 
 a pattern ground shield (PGS) comprising a first portion and a second portion, the PGS underlying the second dielectric layer; 
 a switch for electrically coupling the first portion of the PGS to the second portion of the PGS, wherein the switch is situated in a first substrate; 
 a second substrate above the glue oxide layer; and 
 an interconnect metal above the second substrate. 
 
     
     
       2. The semiconductor device of  claim 1 , comprising:
 a third dielectric layer between the second dielectric layer and the first substrate, wherein a first conductive element extends through the third dielectric layer from the first portion of the PGS to the switch and a second conductive element extends through the third dielectric layer from the second portion of the PGS to the switch. 
 
     
     
       3. The semiconductor device of  claim 2 , wherein the first portion of the PGS and the second portion of the PGS are separated by the third dielectric layer. 
     
     
       4. The semiconductor device of  claim 1 , comprising:
 a third dielectric layer, wherein a bottom surface of the second substrate is in contact with a top surface of the glue oxide layer and a top surface of the second substrate is in contact with a bottom surface of the third dielectric layer. 
 
     
     
       5. The semiconductor device of  claim 4 , wherein the interconnect metal is in contact with a top surface of the third dielectric layer and a sidewall of the third dielectric layer. 
     
     
       6. The semiconductor device of  claim 1 , comprising:
 a third dielectric layer between the second substrate and the interconnect metal. 
 
     
     
       7. The semiconductor device of  claim 6 , wherein the interconnect metal is in contact with a top surface of the third dielectric layer and a sidewall of the third dielectric layer. 
     
     
       8. A semiconductor device, comprising:
 a glue oxide layer; 
 a first inductor underlying the glue oxide layer; 
 a first dielectric layer underlying the first inductor; 
 a pattern ground shield (PGS) comprising a first portion and a second portion, the PGS underlying the first dielectric layer; 
 a switch for electrically coupling the first portion of the PGS to the second portion of the PGS; and 
 an interconnect metal above the glue oxide layer, wherein the interconnect metal is spaced apart from the glue oxide layer by a first substrate. 
 
     
     
       9. The semiconductor device of  claim 8 , wherein the switch is situated in a second substrate. 
     
     
       10. The semiconductor device of  claim 8 , wherein the first inductor is spaced apart from the glue oxide layer by a second dielectric layer. 
     
     
       11. The semiconductor device of  claim 8 , comprising:
 a second dielectric layer, wherein the interconnect metal is above a top surface of the second dielectric layer and adjacent a sidewall of the second dielectric layer. 
 
     
     
       12. The semiconductor device of  claim 8 , comprising:
 a second dielectric layer, wherein a first conductive element extends through the second dielectric layer from the first portion of the PGS to the switch and a second conductive element extends through the second dielectric layer from the second portion of the PGS to the switch. 
 
     
     
       13. The semiconductor device of  claim 12 , wherein the first portion of the PGS and the second portion of the PGS are separated by the second dielectric layer. 
     
     
       14. A semiconductor device, comprising:
 a glue oxide layer; 
 a first inductor underlying the glue oxide layer; 
 a pattern ground shield (PGS) comprising a first portion and a second portion, the PGS underlying the first inductor; 
 a switch for electrically coupling the first portion of the PGS to the second portion of the PGS, wherein the switch is situated in a first substrate; 
 an interconnect metal, wherein the interconnect metal is spaced apart from the first inductor by the glue oxide layer; and 
 a second substrate between the glue oxide layer and the interconnect metal. 
 
     
     
       15. The semiconductor device of  claim 14 , wherein the first portion of the PGS is separated from the second portion of the PGS by a dielectric layer. 
     
     
       16. The semiconductor device of  claim 14 , comprising:
 a dielectric layer between the second substrate and the interconnect metal, wherein a sidewall of the interconnect metal is in contact with a sidewall of the dielectric layer. 
 
     
     
       17. The semiconductor device of  claim 14 , wherein the second substrate is adhered to the glue oxide layer. 
     
     
       18. The semiconductor device of  claim 14 , comprising:
 a dielectric layer in contact with the second substrate and the interconnect metal. 
 
     
     
       19. The semiconductor device of  claim 18 , wherein the second substrate is in contact with the glue oxide layer. 
     
     
       20. The semiconductor device of  claim 14 , wherein the first substrate underlies the PGS.