High performance memory controller

Abstract

A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

What is claimed is: 
     
       1. A memory controller, comprising:
 an input configured to: 
 receive an indication of an internal data validation result that indicates whether a first type of data read of a plurality of types of data reads has a first probability of being successful; and 
 receive data in conjunction with the first type of data read of the plurality of types of data reads when the internal data validation result is determined to have the first probability of being successful; and 
 an error correction code (ECC) component configured to apply an error correction technique to the data consistent with the first type of data read of the plurality of types of data reads when the internal data validation result is determined to have the first probability of being successful. 
 
     
     
       2. The memory controller of  claim 1 , wherein the data comprises data stored in a memory array coupled to the memory controller. 
     
     
       3. The memory controller of  claim 1 , wherein the input is configured to receive second data in conjunction with a second type of data read of the plurality of types of data reads when the internal data validation result is determined to have a second probability of being successful. 
     
     
       4. The memory controller of  claim 3 , wherein the second data comprises data stored in a memory array coupled to the memory controller and soft data associated with the data stored in the memory array. 
     
     
       5. The memory controller of  claim 3 , wherein the ECC component is configured to apply a second error correction technique to the second data consistent with the second type of data read of the plurality of types of data reads when the internal data validation result is determined to have the second probability of being successful. 
     
     
       6. The memory controller of  claim 3 , wherein the input is configured to receive the second data in conjunction with a third type of data read of the plurality of types of data reads when the internal data validation result is determined to have a third probability of being successful. 
     
     
       7. The memory controller of  claim 6 , wherein the memory controller is configured to generate a channel calibration value based on a channel calibration determination of an error introduced to the second data via a data path coupled to the input. 
     
     
       8. The memory controller of  claim 7 , wherein the memory controller is configured to generate the channel calibration value as part of the third type of data read of the plurality of types of data reads. 
     
     
       9. The memory controller of  claim 7 , wherein the memory controller is configured to apply the channel calibration value to the second data to alleviate channel errors in the second data to generate third data. 
     
     
       10. The memory controller of  claim 9 , wherein the ECC component is configured to apply the second error correction technique to the third data consistent with the third type of data read of the plurality of types of data reads when the internal data validation result is determined to have the third probability of being successful. 
     
     
       11. A device, comprising:
 a memory controller, configured to:
 receive an indication of an internal data validation result that indicates a probability of whether a read request type of a plurality of predetermined read request types of data reads of data to be accessed from a memory array will be successful; 
 determine, based upon the indication, which read request type of the plurality of predetermined read request types to execute, wherein respective read request types of the plurality of predetermined read request types are each associated with respective error correction data associated with the data; and 
 utilize the respective error correction data associated with the read request type to correct the data when the data is read in conjunction with a first read request type of the plurality of predetermined read request types. 
 
 
     
     
       12. The device of  claim 11 , wherein the memory controller is configured to execute the first read request type of the plurality of predetermined read request types based on a comparison of the indication with a threshold value. 
     
     
       13. The device of  claim 12 , wherein the memory controller is configured to generate a read request of soft error correction data associated with the data as the error correction data in conjunction with execution of the first read request type. 
     
     
       14. The device of  claim 11 , wherein the memory controller is configured to execute a second read request type of the plurality of predetermined read request types based on a comparison of the indication with a threshold value. 
     
     
       15. The device of  claim 14 , wherein the memory controller is configured to generate a read request of soft error correction data associated with the data when the second read request type is executed. 
     
     
       16. The device of  claim 15 , wherein the memory controller is configured to apply a channel calibration value to the soft error correction data to alleviate channel errors in the soft error correction data to generate second error correction data. 
     
     
       17. The device of  claim 16 , wherein the memory controller is configured to utilize the second error correction data to correct the data when the second read request type is executed. 
     
     
       18. The device of  claim 14 , wherein the memory controller is configured to read no error correction data as the selective reading of error correction data associated with the data when the second read request type has been initiated. 
     
     
       19. A memory device, comprising:
 a memory array comprising data;
 a memory controller coupled to the memory array, wherein the memory controller is configured to: 
 receive an indication of an internal data validation result that indicates the probability that each type of data read of a plurality of types of data reads of the data will be successful; 
 determine which value of a predetermined set of values matches the indication; 
 initiate a first type of data read of the plurality of types of data reads of the data without a read of error correction data associated with the data when a first value of the predetermined set of values matches the indication; and 
 initiate a second type of data read of the plurality of types of data reads of the data with a read of the error correction data associated with the data when a second value of the predetermined set of values matches the indication. 
 
 
     
     
       20. The memory device of  claim 19 , wherein the memory controller is configured to:
 apply a first error correction technique to the data when the first type of data read of the plurality of types of data reads is initiated; and 
 apply a second error correction technique to the data when the second type of data read of the plurality of types of data reads is initiated, wherein the second error correction technique utilizes the error correction data.