Ordering memory requests based on access efficiency

Abstract

An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

What is claimed is: 
     
       1. An apparatus, comprising:
 a memory circuit; and 
 a memory controller circuit, including a write request queue, configured to:
 receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request; 
 schedule a received read request for execution; 
 store a received write request in the write request queue; and 
 reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue; 
 wherein memory access efficiency is determined using a comparison of a number of total clock cycles to a number of active clock cycles used to process memory requests. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the memory controller circuit is further configured to determine a current memory access efficiency in response to a completion of a read turn and a write turn, wherein a read turn corresponds to an execution of a number of read requests, and a write turn corresponds to an execution of a number write requests, and wherein the current memory access efficiency is determined based on a ratio of active clock cycles to total clock cycles during the completed read and write turns. 
     
     
       3. The apparatus of  claim 2 , wherein the memory controller circuit is further configured to modify a number of memory requests to be executed in subsequent read and write turns based on a comparison of the current memory access efficiency to the specified memory access efficiency. 
     
     
       4. The apparatus of  claim 2 , wherein the memory controller circuit is further configured to schedule at least one partial write memory request to be executed between a read turn and a write turn. 
     
     
       5. The apparatus of  claim 1 , wherein the memory controller circuit is further configured to schedule a subset of write requests included in the write request queue in response to a determination that a number of write requests in the write request queue satisfies a threshold number of requests. 
     
     
       6. The apparatus of  claim 5 , wherein the memory controller circuit is further configured to prioritize read requests over write requests by scheduling the subset of write requests to be executed subsequent to execution of a number of read requests. 
     
     
       7. The apparatus of  claim 1 , wherein the memory controller circuit is further configured to prioritize a particular write request over a different write request in response to a determination that an amount of data to be stored by the particular write request is larger than an amount of data to be stored by the different write request. 
     
     
       8. A method comprising:
 receiving, by a memory controller, a memory request to access a memory circuit, wherein the memory controller includes a write request queue and a scheduled request buffer; 
 processing, by the memory controller, the memory request according to whether the memory request is a read request or a write request; 
 determining an efficiency value based on activity of a communication bus during execution of a number of read requests and a number of write requests, wherein the communication bus is coupled between the memory controller and at least one memory circuit and the efficiency value is determined using a ratio of a number of active bus clock cycles used to process memory requests to a total number of bus clock cycles; 
 scheduling the memory request based on the efficiency value and based on a number of write requests stored in the write request queue; and 
 executing, by the memory circuit, scheduled read requests and write requests. 
 
     
     
       9. The method of  claim 8 , wherein the processing includes adding to the write request queue in response to the memory request being a write request. 
     
     
       10. The method of  claim 9 , further comprising scheduling, for execution, a plurality of write requests from the write request queue in response to determining that a number of write requests in the write request queue is greater than a threshold number. 
     
     
       11. The method of  claim 8 , wherein the processing includes scheduling the memory request for execution in response to the memory request being a read request. 
     
     
       12. The method of  claim 8 , further comprising:
 completing a read turn by executing a scheduled number of consecutive read requests; 
 completing a write turn by executing a scheduled number of consecutive write requests; and 
 determining the efficiency value in response to completing a read turn and a write turn. 
 
     
     
       13. The method of  claim 12 , further comprising adjusting a number of memory requests to be executed in a subsequent read turn and write turn based on the determined efficiency value. 
     
     
       14. The method of  claim 8 , further comprising prioritizing write requests based on an amount of data to be stored in the memory circuit by each write request. 
     
     
       15. An apparatus comprising:
 a system interface coupled to at least one processor; 
 an instruction queue configured to store one or more memory requests prior to execution; 
 a write request queue; and 
 an arbitration circuit configured to:
 receive a memory request from the system interface and determine if the memory request includes a read request or a write request; 
 place a received read request into the instruction queue; 
 place a received write request into the write request queue; and 
 reorder memory requests placed in the instruction queue based on achieving a specified level of memory access efficiency, wherein a level of memory access efficiency is determined using a comparison of a number of active bus clock cycles that are used to process memory requests to a total number of bus clock cycles. 
 
 
     
     
       16. The apparatus of  claim 15 , wherein the arbitration circuit is further configured to determine a current level of memory access efficiency in response to a completion of a read turn and a write turn, wherein a read turn corresponds to an execution of a number of read requests, and a write turn corresponds to an execution of a number write requests, and wherein the current level is determined based on a percentage of the total number of bus clock cycles occurring during the completed read and write turns that were used to process memory requests. 
     
     
       17. The apparatus of  claim 16 , wherein the arbitration circuit is further configured to adjust a number of memory requests to be executed in subsequent read and write turns based on a comparison of the current level to the specified level. 
     
     
       18. The apparatus of  claim 16 , wherein the arbitration circuit is further configured to place, in the instruction queue, at least one partial write memory request to be executed between a read turn and a write turn. 
     
     
       19. The apparatus of  claim 15 , wherein the arbitration circuit is further configured to, in response to a determination that a number of write requests in the write request queue satisfies a threshold number of requests, place, in the instruction queue, a subset of write requests included in the write request queue, wherein scheduled read requests are prioritized for execution over the subset of write requests. 
     
     
       20. The apparatus of  claim 15 , wherein the arbitration circuit is further configured to prioritize a particular write request over a different write request in response to a determination that an amount of data to be stored by the particular write request is larger than an amount of data to be stored by the different write request.