Multi-channel DIMMs

Abstract

A system and method for multi-channel communication with dual in-line memory modules (“DIMMs”) is disclosed. The system retrieves information characterizing a plurality of memory channels, each of each is configurable to facilitate data communication between a DIMM and a memory controller with associated memory channel interfaces. Based on the retrieved information, one of the memory channels is designated as the active memory channel, granting the designated memory channel the ability to issue memory requests or transactions to the DIMM. On a periodic or as-needed basis (e.g., when the active memory channel is stalled or nearly stalled), the system determines whether to designate a different of the memory channels as the active memory channel, thereby enabling the newly-designated active memory channel the ability to issue memory requests or transactions to the DIMM. In some embodiments, only one of the memory channels is active at a time for communication with each DIMM.

We claim: 
     
       1. A computer-implemented method, comprising:
 retrieving, at a computing system, information characterizing a plurality of memory channels, wherein: 
 the plurality of memory channels comprises at least a first memory channel and a second memory channel; 
 each of the plurality of memory channels comprises a memory controller buffer; 
 each of the plurality of memory channels is configurable to facilitate memory transactions between a memory module and a memory controller of the computing system; 
 each of the plurality of memory channels has previously been designated as an active memory channel, the active memory channel being currently configured to receive new memory transactions issued by the memory controller; 
 the first memory channel is currently designated as the active memory channel; and 
 the information comprises, for each of the plurality of memory channels, a number of clock cycles since the memory channel was last the active memory channel or a fill level of the memory controller buffer of the memory channel; 
 determining, based on the information, whether to change which of the plurality of memory channels is designated as the active memory channel; 
 responsive to the determination, selecting, based on the information, the second memory channel as a next active memory channel to receive new memory transactions issued by the memory controller based on at least one of:
 for each of the plurality of memory channels, the number of cycles since the memory channel was last the active memory channel and the second memory channel having the greatest number of cycles since last being the active memory channel; or 
 for each of the plurality of memory channels, the fill level of the memory controller buffer of the memory channel; and 
 
 designating the second memory channel as the active memory channel currently configured to receive new memory transactions issued by the memory controller. 
 
     
     
       2. The method of  claim 1 , wherein the information characterizing the plurality of memory channels further comprises, for each of the plurality of memory channels, a number of clock cycles the memory channel has been the active memory channel or a number of pending memory transactions associated with the memory channel. 
     
     
       3. The method of  claim 2 , wherein the selection of the second memory channel as the next active memory channel is based on, for each of the plurality of memory channels, the fill level of the memory controller buffer of the memory channel. 
     
     
       4. The method of  claim 1 , wherein determining whether to change which of the plurality of memory channels is designated as the active memory channel is based on whether the number of clock cycles the first memory channel has been active exceeds a threshold number of clock cycles. 
     
     
       5. The method of  claim 1 , wherein determining whether to change which of the plurality of memory channels is designated as the active memory channel is based on the fill level of the memory controller buffer of the first memory channel. 
     
     
       6. The method of  claim 1 , wherein the selection of the second memory channel as the next active memory channel is based on:
 for each of the plurality of memory channels, the number of cycles since the memory channel was last the active memory channel; and 
 the second memory channel having the greatest number of cycles since last being the active memory channel. 
 
     
     
       7. The method of  claim 1 , wherein at most one of the plurality of memory channels is designated as the active memory channel at a time. 
     
     
       8. The method of  claim 1 , wherein designating the second memory channel as the active memory channel comprises configuring the memory controller to use the second memory channel for communication with the memory module. 
     
     
       9. The method of  claim 1 , wherein each of the plurality of memory channels comprises:
 an input buffer; and 
 an output buffer. 
 
     
     
       10. The method of  claim 9 , wherein the plurality of memory channel interfaces share a physical interconnect between the memory controller and the memory module. 
     
     
       11. The method of  claim 10 , wherein designating the second memory channel as the active memory channel comprises configuring the associated memory channel interface for exclusive use of the shared physical interconnect. 
     
     
       12. The method of  claim 1  wherein the fill level of the memory controller buffer of each of the plurality of memory channels is a fill level of the memory controller over a number of clock cycles. 
     
     
       13. A system, comprising:
 a memory module configured to store data received at a memory module interface, and to provide data to the memory module interface, in response to memory requests received at the memory module interface; 
 a memory controller configured to issue memory transactions to the memory module; 
 a plurality of memory channels, wherein:
 each of the plurality of memory channels comprises a memory controller buffer; 
 each of the plurality of memory channels is configured to facilitate memory transactions between the memory controller and the memory module; and 
 each of the plurality of memory channels has previously been designated as an active memory channel, the active memory channel being currently configured to receive new memory transactions issued by the memory controller; 
 
 a shared physical interconnect between the memory module and each of the plurality of memory channels; and 
 a first component configured to:
 designate a memory channel, from the plurality of memory channels, as the active memory channel, wherein the active memory channel is enabled to provide data to the memory module or consume data from the memory module over the shared physical interconnect; and 
 determine whether to change which of the plurality of memory channels is designated as the active memory channel based on at least one of:
 for each of the plurality of memory channels, a number of cycles since the memory channel was last the active memory channel and at least one of the plurality of memory channels having the greatest number of cycles since last being the active memory channel; or 
 a fill level of the memory controller buffer of the active memory channel. 
 
 
 
     
     
       14. The system of  claim 13  further comprising a clock signal, where the determination of whether to change which of the plurality of memory channels is designated as the active memory channel occurs every cycle of the clock signal. 
     
     
       15. The system of  claim 13 , wherein the first component is further configured to determine a number of clock cycles the designated memory channel has been the active memory channel, and wherein the determination of whether to change which of the plurality of memory channels is designated as the active memory channel is further based on whether the determined number of clock cycles exceeds a threshold number of clock cycles. 
     
     
       16. The system of  claim 13 , wherein at most one of the plurality of memory channels is designated as the active memory channel at a time. 
     
     
       17. The system of  claim 16 , wherein designating a memory channel as the active memory channel comprises configuring the memory channel for exclusive use of the shared physical interconnect. 
     
     
       18. The system of  claim 13 , wherein the fill level of the memory controller buffer of each of the plurality of memory channels is a fill level of the memory controller over a number of clock cycles. 
     
     
       19. A computer-readable storage device storing computer-readable instructions, the instructions comprising:
 instructions for retrieving, at a computing system, information characterizing a plurality of memory channels, wherein:
 the plurality of memory channels comprises at least a first memory channel and a second memory channel; 
 each of the plurality of memory channels comprises a memory controller buffer; 
 each of the plurality of memory channels is configurable to facilitate memory transactions between a memory module and a memory controller of the computing system; 
 each of the plurality of memory channels has previously been designated as an active memory channel, the active memory channel being currently configured to receive new memory transactions issued by the memory controller; and 
 the information comprises, for each of the plurality of memory channels, a number of clock cycles since the memory channel was last the active memory channel or a fill level of the memory controller buffer of the memory channel; 
 
 instructions for designating the first memory channel as the active memory channel; 
 instructions for determining, based on the information, whether to change which of the
 plurality of memory channels is designated as the active memory channel; 
 
 responsive to the determination, instructions for selecting, based on the information, the second memory channel as a next active memory channel to receive new memory transactions issued by the memory controller based on at least one of:
 for each of the plurality of memory channels, the number of cycles since the memory channel was last the active memory channel and the second memory channel having the greatest number of cycles since last being the active memory channel; or 
 for each of the plurality of memory channels, the fill level of the memory controller buffer of the memory channel; and 
 
 instructions for designating the second memory channel as the active memory channel currently configured to receive new memory transactions issued by the memory controller. 
 
     
     
       20. The computer-readable storage device of  claim 19 , wherein the information characterizing the plurality of memory channels comprises, for each of the plurality of memory channels, a number of clock cycles the memory channel has been the active memory channel or a number of pending memory transactions associated with the memory channel.