P
US10693447B1ActiveUtilityPatentIndex 70

Comparator circuit

Assignee: ARTERY TECH CO LTDPriority: Apr 24, 2019Filed: Oct 31, 2019Granted: Jun 23, 2020
Est. expiryApr 24, 2039(~12.8 yrs left)· nominal 20-yr term from priority
Inventors:HAO BAOTIANWANG WEITIELI CHAO
H03K 5/2409H03K 5/2481H03K 5/2472
70
PatentIndex Score
2
Cited by
5
References
10
Claims

Abstract

A comparator circuit includes: a comparator, coupled between a power voltage and a ground voltage, configured to perform a comparison according to a set of input signals to generate a comparison signal; a current source; and positive feedback circuits. The comparator circuit includes a set of input terminals and sets of transistors respectively coupled between a power voltage and a node or a ground voltage. The positive feedback circuits perform positive feedback operations on the node to generate instant currents on the node, to make the comparator switch the comparison signal in response to transition of the set of input signals in real time. Any of the positive feedback circuits includes: a first switch, configured to enable or disable said any positive feedback circuit in response to transition of the comparison signal; and a set of transistors, configured to generate a second current corresponding to the first current.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A comparator circuit, comprising:
 a comparator, coupled between a power voltage and a ground voltage, configured to perform a comparison according to a set of input signals to generate at least one comparison signal, wherein the comparator comprises:
 a set of input terminals, configured to receive the set of input signals; 
 a first set of transistors, coupled between the power voltage and a node, wherein a first terminal, a second terminal and a control terminal of a transistor within the first set of transistors are respectively coupled to a second terminal of another transistor within the first set of transistors, the node and an input terminal within the set of input terminals, and a first terminal of the other transistor within the first set of transistors is coupled to the power voltage; 
 a second set of transistors, coupled between the power voltage and the node, wherein a first terminal, a second terminal and a control terminal of a transistor within the second set of transistors are respectively coupled to a second terminal of another transistor within the second set of transistors, the node and another input terminal within the set of input terminals, and a first terminal of the other transistor within the second set of transistors is coupled to the power voltage; 
 a third set of transistors, coupled between the power voltage and the ground voltage, wherein a first terminal, a second terminal and a control terminal of a transistor within the third set of transistors are respectively coupled to a second terminal of another transistor within the third set of transistors, the ground voltage and an output stage of the comparator, and a first terminal and a control terminal of the other transistor within the third set of transistors are respectively coupled to the power voltage and a control terminal of the other transistor within the first set of transistors; and 
 a fourth set of transistors, coupled between the power voltage and the ground voltage and positioned in the output stage, wherein a first terminal, a second terminal and a control terminal of a transistor within the fourth set of transistors are respectively coupled to a second terminal of another transistor within the fourth set of transistors, the ground voltage and the control terminal of the transistor within the third set of transistors, and a first terminal and a control terminal of the other transistor within the fourth set of transistors are respectively coupled to the power voltage and a control terminal of the other transistor within the second set of transistors; 
 
 a current source, coupled between the node and the ground voltage, configured to provide current; and 
 a plurality of positive feedback circuits, coupled between the power voltage and the ground voltage and coupled to the node, configured to perform a plurality of positive feedback operations on the node to generate a plurality of instant currents on the node, respectively, to make the comparator switch said at least one comparison signal in response to a transition of the set of input signals in real time, wherein any positive feedback circuit within the positive feedback circuits comprises:
 a first switch, coupled to the node, configured to enable or disable said any positive feedback circuit in response to a transition of said at least one comparison signal, wherein when said any positive feedback circuit is enabled, a first current flows through the first switch; and 
 a set of transistors, coupled between the power voltage and the ground voltage, configured to generate the first current and a second current corresponding to each other, wherein an instant current within the instant currents corresponds to the second current. 
 
 
     
     
       2. The comparator circuit of  claim 1 , wherein when said any positive feedback circuit is enabled, the second current flows through a first transistor and a second transistor within the set of transistors, and the first current flows through a third transistor within the set of transistors. 
     
     
       3. The comparator circuit of  claim 2 , wherein a first terminal, a second terminal and a control terminal of the first transistor are respectively coupled to a second terminal of the second transistor, the ground voltage and a control terminal of the third transistor, and a first terminal and a control terminal of the second transistor are respectively coupled to the power voltage and the control terminal of the other transistor within the first set of transistors. 
     
     
       4. The comparator circuit of  claim 3 , wherein the first terminal and the control terminal of the first transistor are coupled to each other, to make the first transistor be configured as a diode-connected transistor; and a ratio of respective specific parameters of the third transistor and the first transistor is equal to n, to make the first current flowing through the third transistor be n times the second current flowing through the first transistor, wherein n is greater than one. 
     
     
       5. The comparator circuit of  claim 2 , wherein a first terminal, a second terminal and a control terminal of the first transistor are respectively coupled to a second terminal of the second transistor, the ground voltage and a control terminal of the third transistor, and a first terminal and a control terminal of the second transistor are respectively coupled to the power voltage and the control terminal of the other transistor within the second set of transistors. 
     
     
       6. The comparator circuit of  claim 5 , wherein the first terminal and the control terminal of the first transistor are coupled to each other, to make the first transistor be configured as a diode-connected transistor; and a ratio of respective specific parameters of the third transistor and the first transistor is equal to n, to make the first current flowing through the third transistor be n times the second current flowing through the first transistor, wherein n is greater than one. 
     
     
       7. The comparator circuit of  claim 2 , wherein a first terminal and a second terminal of the third transistor are respectively coupled to the first switch and the ground voltage. 
     
     
       8. The comparator circuit of  claim 2 , wherein said any positive feedback circuit comprises:
 a second switch, coupled between the first transistor and the second transistor, configured to enable or disable said any positive feedback circuit in response to the transition of said at least one comparison signal, wherein when said any positive feedback circuit is enabled, the second current flows through the second switch. 
 
     
     
       9. The comparator circuit of  claim 1 , wherein the positive feedback circuits comprise:
 a first positive feedback circuit, coupled between the power voltage and the node, configured to perform a first positive feedback operation within the positive feedback operations on the node to generate a first instant current within the instant currents on the node; and 
 a second positive feedback circuit, coupled between the power voltage and the node, configured to perform a second positive feedback operation within the positive feedback operations on the node to generate a second instant current within the instant currents on the node; 
 wherein the first instant current and the second instant current respectively correspond to a first transition and a second transition of the set of input signals. 
 
     
     
       10. The comparator circuit of  claim 1 , wherein the control terminal and the second terminal of the other transistor within the first set of transistors are coupled to each other, to make the other transistor within the first set of transistors be configured as a diode-connected transistor; and the control terminal and the second terminal of the other transistor within the second set of transistor are coupled to each other, to make the other transistor within the second set of transistors be configured as a diode-connected transistor.

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