Method and device for synthesizing a circuit layout

Abstract

A method for synthesizing a circuit layout, characterized by the following features: primary circuit functions are placed on the circuit layout; secondary circuit functions are placed on the circuit layout; at least one first mask is generated in such a way that the first mask reproduces the primary circuit functions and covers the secondary circuit functions when a semiconductor substrate is structured according to the circuit layout by way of the first mask; and the placement of the circuit functions takes place in such a way that at least one changed mask reproduces the primary circuit functions and the secondary circuit functions when the semiconductor substrate is structured according to the circuit layout by way of at least one second mask.

What is claimed is: 
     
       1. A method for synthesizing a circuit layout, comprising:
 placing primary circuit functions on the circuit layout; 
 placing secondary circuit functions on the circuit layout; 
 after the placing of the primary circuit functions and the placing of the secondary circuit functions, generating, using the circuit layout which includes the primary circuit functions and the secondary circuit functions, at least one first mask, the first mask configured to reproduce the primary circuit functions and not the secondary circuit functions; 
 after the generating of the first mask, structuring a first semiconductor substrate using the first mask to implement, on the first semiconductor substrate, the primary circuit functions and not the secondary circuit functions; and 
 after the generating of the first mask, generating, using the circuit layout which includes the primary circuit functions and the secondary circuit functions, at least one second mask, the second mask configured to reproduce the primary circuit functions and the secondary circuit functions. 
 
     
     
       2. The method as recited in  claim 1 , wherein the placement of the primary circuit functions includes the placement of at least one processor core, the placement of the primary circuit functions includes the placement of at least one peripheral function, the at least one peripheral function being a serial peripheral interface or a CAN controller, and the placement of the primary circuit functions includes the placement of at least one memory. 
     
     
       3. The method as recited in  claim 2 , wherein the placement of the memory includes the placement of an electrically erasable programmable read-only memory including a flash EEPROM, and the placement of the memory includes the placement of a random-access memory. 
     
     
       4. The method as recited in  claim 1 , wherein the placement of the secondary circuit functions includes the placement of at least one peripheral function, the at least one peripheral function including a serial peripheral interface or a CAN controller, and the placement of the secondary circuit functions includes the placement of interconnected basic CMOS-synthesis gates. 
     
     
       5. The method as recited in  claim 4 , wherein the placement of the basic CMOS-synthesis gates includes the placement of at least one of the following elements: (i) a NOT gate, (ii) a NAND gate, (iii) a NOR gate, (iv) a state-controlled flip-flop, in particular a D-latch, and (v) a pulse edge controlled flip-flop, the pulse edge controlled flip-flop including a register. 
     
     
       6. The method as recited in  claim 1 , wherein the secondary circuit functions include logic for a CAN controller. 
     
     
       7. A non-transitory machine-readable memory medium on which is stored a computer program for synthesizing a circuit layout, the computer program, when executed by a processor, causing the processor to perform:
 placing primary circuit functions on the circuit layout; 
 placing secondary circuit functions on the circuit layout; 
 after the placing of the primary circuit functions and the placing of the secondary circuit functions, generating, using the circuit layout which includes the primary circuit functions and the secondary circuit functions, at least one first mask, the first mask configured to reproduce the primary circuit functions and not the secondary circuit functions; 
 after the generating of the first mask, structuring a first semiconductor substrate using the first mask to implement, on the first semiconductor substrate, the primary circuit functions and not the secondary circuit functions; and 
 after the generating of the first mask, generating, using the circuit layout which includes the primary circuit functions and the secondary circuit functions, at least one second mask, the second mask configured to reproduce the primary circuit functions and the secondary circuit functions. 
 
     
     
       8. The non-transitory machine-readable memory medium as recited in  claim 7 , wherein the secondary circuit functions include logic for a CAN controller.