Pooled frontline ECC decoders in memory systems

Abstract

Various implementations described herein relate to systems and methods for correcting data from memory systems such as a plurality of non-volatile memory devices of a Solid State Drive (SSD), including but not limited to, receiving frames of the data from the plurality of non-volatile memory devices, allocating the frames among pooled frontline Error Correction Code (ECC) decoders, decoding, by the pooled frontline ECC decoders, the frames to output first decoded frames, and returning the first decoded frames to the read channels.

What is claimed is: 
     
       1. A method for correcting data read from a plurality of non-volatile memory devices of a memory system and stored in a memory buffer, the method comprising:
 receiving, by an arbiter via a plurality of read channels, frames of the data from the plurality of non-volatile memory devices, wherein all of the frames received are coded; 
 allocating, by the arbiter, the frames among a plurality of pooled frontline Error Correction Code (ECC) decoders; 
 decoding, by the plurality of pooled frontline ECC decoders, the frames to output first decoded frames; and 
 storing, by the plurality of pooled frontline ECC decoders, the first decoded frames into the memory buffer. 
 
     
     
       2. The method of  claim 1 , further comprising:
 determining that the plurality of pooled frontline ECC decoders failed to decode some of the frames; 
 storing the some of the frames into the memory buffer for access by a plurality of second-line ECC decoders; 
 decoding, by the plurality of second-line ECC decoders, the some of the frames to output second decoded frames; and 
 storing, by the plurality of second-line ECC decoders, the second decoded frames into the memory buffer. 
 
     
     
       3. The method of  claim 1 , further comprising:
 determining that the plurality of pooled frontline ECC decoders and a plurality of second-line ECC decoders failed to decode some of the frames; 
 storing the some of the frames into a plurality of third-line ECC decoders; 
 decoding, by the plurality of third-line ECC decoders, the some of the frames to output third decoded frames; and 
 storing, by the plurality of third-line ECC decoders, the third decoded frames into the memory buffer. 
 
     
     
       4. The method of  claim 1 , wherein the plurality of pooled frontline ECC decoders is outside of the plurality of read channels. 
     
     
       5. The method of  claim 1 , further comprising updating at least one of the plurality of pooled frontline ECC decoders while others of the plurality of pooled frontline ECC decoders are decoding the frames. 
     
     
       6. The method of  claim 1 , wherein the frames are allocated among the plurality of pooled frontline ECC decoders based on availability of the pooled frontline ECC decoders, types of code data of the frames, and types of codes supported by the pooled frontline ECC decoders. 
     
     
       7. The method of  claim 6 , wherein
 a first frame of the plurality of frames has a type of code data corresponding to a type of codes supported by a first pooled frontline ECC decoder; 
 the first pooled frontline ECC decoder is available; and 
 the first frame is allocated to be decoded by the first pooled frontline ECC decoder. 
 
     
     
       8. The method of  claim 1 , wherein
 the frames comprise a first frame and a second frame received from a same one of the plurality of read channels; and 
 allocating the frames among the plurality of pooled frontline ECC decoders comprises allocating the first frame to a first one of the plurality of pooled frontline ECC decoders and allocating the second frame to a second one of the plurality of pooled frontline ECC decoders. 
 
     
     
       9. The method of  claim 8 , wherein the first one of the plurality of pooled frontline ECC decoders and the second one of the plurality of pooled frontline ECC decoders support different codes. 
     
     
       10. The method of  claim 8 , wherein the first one of the plurality of pooled frontline ECC decoders and the second one of the plurality of pooled frontline ECC decoders support same codes. 
     
     
       11. A memory controller of a memory system, comprising:
 a plurality of pooled frontline Error Correction Code (ECC) decoders configured to decode data read from a plurality of non-volatile memory devices; 
 a plurality of subsequent ECC decoders configured to decode data failed to be decoded by the plurality of pooled frontline ECC decoders; and 
 an arbiter operatively coupled to a plurality of read channels, wherein the arbiter is configured to:
 receive, via the plurality of read channels, frames of the data from the plurality of non-volatile memory devices, and 
 allocate the frames among the plurality of pooled frontline ECC decoders. 
 
 
     
     
       12. The memory controller of  claim 11 , wherein the plurality of pooled frontline ECC decoders is outside of a plurality of read channels. 
     
     
       13. The memory controller of  claim 11 , wherein the arbiter allocates the frames among the plurality of pooled frontline ECC decoders based on availability of the pooled frontline ECC decoders, types of code data of the frames, and types of codes supported by the pooled frontline ECC decoders. 
     
     
       14. The memory controller of  claim 11 , wherein
 at least one of the plurality of pooled frontline ECC decoders is updated while others of the plurality of pooled frontline ECC decoders are decoding the frames. 
 
     
     
       15. A memory system, comprising:
 a first plurality of non-volatile memory devices; 
 a memory controller, comprising:
 a first plurality of pooled frontline Error Correction Code (ECC) decoders configured to decode data stored by the first plurality of non-volatile memory devices; 
 a plurality of subsequent ECC decoders configured to decode data failed to be decoded by the first plurality of pooled frontline ECC decoders; 
 a first arbiter operatively coupled to the first plurality of read channels, wherein the first arbiter is configured to:
 receive, via the first plurality of read channels, first frames of the data from the first plurality of non-volatile memory devices, and 
 allocate the first frames among the first plurality of pooled frontline ECC decoders; and 
 
 
 a first plurality of read channels operatively coupled to the first plurality of non-volatile memory devices and the memory controller. 
 
     
     
       16. The memory system of  claim 15 , further comprising:
 a second plurality of non-volatile memory devices; 
 a second plurality of read channels operatively coupled to the second plurality of non-volatile memory devices and the memory controller, wherein
 the memory controller further comprises a second plurality of pooled frontline ECC decoders configured to decode data stored by the second plurality of non-volatile memory devices. 
 
 
     
     
       17. The memory system of  claim 16 , wherein the memory controller further comprises a second arbiter operatively coupled to the second plurality of read channels, wherein the second arbiter is configured to:
 receive, via the second plurality of read channels, second frames of the data from the second plurality of non-volatile memory devices; and 
 allocate the second frames among the second plurality of pooled frontline ECC decoders.