Wide band gap device integrated circuit architecture on engineered substrate

Abstract

A method includes forming a wide band gap (WBG) epitaxial layer on an engineered substrate. The WBG epitaxial layer includes a plurality of groups of epitaxial layers. The engineered substrate includes engineered layers formed on a bulk material having a coefficient of thermal expansion (CTE) matching a CTE of the WBG epitaxial layer. The method also includes forming a plurality of WBG devices based on the plurality of groups of epitaxial layers by: for each respective WBG device, forming internal interconnects and electrodes within a respective group of epitaxial layers. The method further includes forming external interconnects between the electrodes of different WBG devices of the plurality of WBG devices to form an integrated circuit.

What is claimed is: 
     
       1. A method of forming semiconductor devices, the method comprising:
 forming a wide band gap (WBG) epitaxial layer on an engineered substrate, wherein the WBG epitaxial layer includes a plurality of groups of epitaxial layers, and wherein the engineered substrate includes engineered layers formed on a bulk material, the bulk material having a coefficient of thermal expansion (CTE) matching a CTE of the WBG epitaxial layer; 
 forming a first WBG device based on a first group of epitaxial layers among the plurality of groups of epitaxial layers by forming a first set of internal interconnects and a first set of electrodes; 
 forming a second WBG device based on a second group of epitaxial layers among the plurality of groups of epitaxial layers by forming a second set of internal interconnects and a second set of electrodes; and 
 forming one or more external interconnects between at least one of the first set of electrodes and at least one of the second set of electrodes. 
 
     
     
       2. The method of  claim 1  wherein the WBG epitaxial layer formed on the engineered substrate have a thickness of at least 10 microns. 
     
     
       3. The method of  claim 1  wherein the engineered substrate is characterized by a diameter of at least 150 millimeters. 
     
     
       4. The method of  claim 1  wherein:
 the WBG epitaxial layer comprises gallium nitride (GaN); and 
 the bulk material of the engineered substrate comprises aluminum nitride (AlN). 
 
     
     
       5. The method of  claim 4  wherein the engineered layers of the engineered substrate comprises at least one of oxide, nitride, or polysilicon. 
     
     
       6. The method of  claim 1  wherein the second group of epitaxial layers is located on top of the first group of epitaxial layers. 
     
     
       7. The method of  claim 6  further comprising:
 etching through a lateral section of the second group of epitaxial layers down to the first group of epitaxial layers. 
 
     
     
       8. The method of  claim 6  further comprising etching a mesa vertically between the first set of electrodes and the second set of electrodes through the WBG epitaxial layer to laterally isolate the first WBG device from the second WBG device. 
     
     
       9. The method of  claim 6  wherein the WBG epitaxial layer further comprises a WBG isolation layer disposed between the first group of epitaxial layers and the second group of epitaxial layers. 
     
     
       10. The method of  claim 1  further comprising masking regions of a group of epitaxial layers of the plurality of groups of epitaxial layers previously formed on the engineered substrate to prevent a subsequent group of epitaxial layers of the plurality of groups of epitaxial layers from being formed in the masked regions of the previously formed group of epitaxial layers. 
     
     
       11. The method of  claim 1  further comprising forming a buffer layer on the engineered substrate before forming the WBG epitaxial layer. 
     
     
       12. The method of  claim 1  wherein:
 forming the first WBG device comprises forming one or more mesas within the first group of epitaxial layers; and 
 at least one of the first set of internal interconnects is formed within a respective one of the one or more mesas of the first WBG device. 
 
     
     
       13. The method of  claim 12  wherein:
 forming the second WBG device comprises forming one or more second mesas within the second group of epitaxial layers; and 
 at least one of the second set of internal interconnects is formed within a respective one of the one or more second mesas of the second WBG device. 
 
     
     
       14. A method of forming semiconductor devices, the method comprising:
 forming a wide band gap (WBG) epitaxial layer on an engineered substrate, wherein the WBG epitaxial layer includes a plurality of groups of epitaxial layers, and wherein the engineered substrate includes engineered layers formed on a bulk material, the bulk material having a coefficient of thermal expansion (CTE) matching a CTE of the WBG epitaxial layer; 
 forming a first WBG device based on a first group of epitaxial layers among the plurality of groups of epitaxial layers; and 
 forming a second WBG device based on a second group of epitaxial layers among the plurality of groups of epitaxial layers, the second group of epitaxial layers formed on top of the first group of epitaxial layers; 
 wherein the first WBG device comprises a high electron mobility transistor (HEMT), and the second WBG device comprises a light emitting diode (LED). 
 
     
     
       15. The method of  claim 14  wherein forming the first WBG device comprises forming one or more first internal interconnects and one or more first electrodes within the first group of epitaxial layers. 
     
     
       16. The method of  claim 15  wherein forming the second WBG device comprises forming one or more second internal interconnects and one or more second electrodes within the second group of epitaxial layers. 
     
     
       17. The method of  claim 16  further comprising:
 forming one or more external interconnects between the one or more first electrodes and the one or more second electrodes to connect the first WBG device and the second WBG device. 
 
     
     
       18. The method of  claim 14  wherein the second group of epitaxial layers comprises multiple quantum wells (MQWs). 
     
     
       19. The method of  claim 14  wherein forming the WBG epitaxial layer comprises:
 forming the first group of epitaxial layers on the engineered substrate; 
 masking a region of the first group of epitaxial layers while exposing a second region of the first group of epitaxial layers; and 
 forming the second group of epitaxial layers on the second region of the first group of epitaxial layers. 
 
     
     
       20. The method of  claim 19  wherein forming the WBG epitaxial layer further comprises forming a WBG isolation layer between the first group of epitaxial layers and the second group of epitaxial layers. 
     
     
       21. The method of  claim 14  further comprising forming a buffer layer on the engineered substrate before forming the WBG epitaxial layer.