Secure feature and key management in integrated circuits

Abstract

A mechanism for providing secure feature and key management in integrated circuits is described. An example integrated circuit includes a secure memory to store a secret key, and a security manager core, coupled to the secure memory, to receive a digitally signed command, verify a signature associated with the command using the secret key, and configure operation of the integrated circuit using the command.

What is claimed is: 
     
       1. A method comprising:
 receiving, by a security manager core of an integrated circuit, a digitally signed message comprising a signature and feature update information, the feature update information comprising a command that, when executed by the security manager core; enables the security manager core to update a functionality of a hardware feature of the integrated circuit to be at least one of locked, unlocked, or modified; 
 obtaining, by the security manager core, a secret key from a secure memory of the integrated circuit; 
 verifying, by the security manager core, the signature of the digitally signed message using the secret key; and 
 executing, by the security manager core, the command to update the functionality of the hardware feature when the signature is verified, wherein the executing the command comprises:
 sending, by the security manager core, a first signal to the hardware feature to lock the functionality of the hardware feature when the feature update information specifies the functionality is to be locked; 
 sending, by the security manager core, a second signal to the hardware feature to unlock the functionality of the hardware feature when the feature update information specifies the functionality is to be unlocked; or 
 sending, by the security manager core, a third signal to the hardware feature to modify the functionality of the hardware feature when the feature update information specifies the functionality is to be modified, wherein the command is associated with an encrypted payload; 
 
 deriving, by the security manager core, a mixed key using a base key accessible to the security manager core; 
 deriving, by the security manager core, a transport key using the mixed key; 
 decrypting, by the security manager core, the encrypted payload using the transport key to obtain a decrypted payload; and 
 delivering, by the security manager core, the decrypted payload to the hardware feature. 
 
     
     
       2. The method of  claim 1  wherein executing the command further comprises
 updating, by the security manager core, a state of the hardware feature, wherein the updating the state of the hardware feature causes at least one of: locking the functionality of the hardware feature, unlocking the functionality of the hardware feature, or modifying the functionality of the hardware feature. 
 
     
     
       3. The method of  claim 2 , wherein an update to the state of the hardware feature by the updating the state is persistent. 
     
     
       4. The method of  claim 1 , wherein executing the command further comprises
 delivering, by the security manager core, one or more keys to one or more components of the integrated circuit, wherein the keys pertain to at least one of: encryption operations of the components, digital rights management operations of the components, password management operations of the components, or authentication operations of the components. 
 
     
     
       5. The method of  claim 1 , wherein executing the command further comprises
 identifying, by the security manager core, one or more hardware constants and storing the hardware constants in designated storage, the hardware constants comprising at least one of: a product chip identifier, one or more security keys, one or more base keys, or error correction data. 
 
     
     
       6. The method of  claim 1 , wherein the digitally signed message is signed by a root authority, and the secret key is a public key of the root authority. 
     
     
       7. The method of  claim 1 , wherein the digitally signed message is signed by a delegate authority. 
     
     
       8. The method of  claim 7 , wherein the verifying the signature associated with the digitally signed command comprises:
 obtaining, by the security manager core, delegate permissions and a public key of the delegate authority from a root signed block signed by a root authority; 
 determining, by the security manager core, that the signature associated with the digitally signed message is valid using the public key of the delegate authority; and 
 determining, by the security manager core, that the command is permitted using the delegate permissions. 
 
     
     
       9. An integrated circuit comprising:
 a secure memory to store a secret key; 
 a security manager (SM) core coupled to the secure memory, the SM core to:
 receive a digitally signed message comprising a signature and a command that, when executed by the security manager core enables the security manager core to update a functionality of a hardware feature of the integrated circuit to be at least one of locked, unlocked, or modified; 
 verify the signature of the digitally signed message using the secret key; and 
 execute the command to update the functionality of the hardware feature when the signature is verified, wherein the SM core, in connection with execution of the command, is to:
 send a first signal to the hardware feature to lock the functionality of the hardware feature when the feature update information specifies the functionality is to be locked; 
 send a second signal to the hardware feature to unlock the functionality of the hardware feature when the feature update information specifies the functionality is to be unlocked; and 
 send a third signal to the hardware feature to modify the functionality of the hardware feature when the feature update information specifies the functionality is to be modified; 
 
 
 an extractor coupled to the SM core; and 
 a plurality of sub-extractors coupled to the extractor, wherein each of the plurality of sub-extractors is also coupled to one of the plurality of hardware features. 
 
     
     
       10. The integrated circuit of  claim 9  further comprising a plurality of hardware features configurable by the SM core. 
     
     
       11. The integrated circuit of  claim 9 , wherein the SM core comprises:
 a crypto module to verify the signature of the digitally signed message; 
 an execution engine module to execute the command; 
 a communications module to facilitate communications between the SM core and the plurality of hardware features of the integrated circuit; and 
 a data storage module to manage internal storage of the SM core and to interface with the secure memory.