Semiconductor device and method for fabricating the same

Abstract

A method for fabricating a semiconductor device includes sequentially laminating a separation layer and a first substrate layer on a sacrificial substrate, and forming a heat dissipation plate comprising a first region and a second region on the first substrate layer. The method further includes removing the sacrificial substrate and the separation layer, and patterning the first substrate layer to form a first substrate exposing the heat dissipation plate in the second region and contacting the heat dissipation plate in the first region, and forming a first element on the first substrate. The method still further includes forming a plurality of conductive pads disposed on the heat dissipation plate in the second region and a first line connecting at least one of the plurality of conductive pads to the first element, and forming a second element on the conductive pads in the second region.

What is claimed is: 
     
       1. A method for fabricating a semiconductor device, the method comprising:
 sequentially laminating a separation layer and a first substrate layer on a sacrificial substrate; 
 forming a heat dissipation plate comprising a first region and a second region on the first substrate layer; 
 removing the sacrificial substrate and the separation layer; 
 patterning the first substrate layer to form a first substrate exposing the heat dissipation plate in the second region and contacting the heat dissipation plate in the first region; 
 forming a first element on the first substrate; 
 forming a plurality of conductive pads disposed on the heat dissipation plate in the second region and a first line connecting at least one of the plurality of conductive pads to the first element; and 
 forming a second element on the conductive pads in the second region. 
 
     
     
       2. The method of  claim 1 , wherein the first substrate layer comprises a silicon layer, and the separation layer comprises a silicon oxide layer, and
 the sequentially laminating of the separation layer and the first substrate layer on the sacrificial substrate is performed by preparing a silicon on insulator (SOI) substrate. 
 
     
     
       3. The method of  claim 1 , wherein the forming of the heat dissipation layer comprises depositing diamond. 
     
     
       4. The method of  claim 1 , further comprising decreasing a thickness of the first substrate layer before the forming of the heat dissipation plate. 
     
     
       5. The method of  claim 1 , wherein the forming of the second element on the conductive pads in the second region is performed by a flip-chip bonding manner. 
     
     
       6. The method of  claim 5 , wherein the second element comprises a second substrate and second electrodes disposed on the second substrate and spaced apart from each other, and the method further comprises:
 connecting the second element to the conductive pads in the second region the connecting comprising interposing a solder layer to connect the conductive pads to the second electrodes. 
 
     
     
       7. The method of  claim 1 , wherein the heat dissipation plate further comprises a third region spaced apart from the first region with the second region between the first region and the third region, and
 the patterning of the first substrate layer further comprises forming a second substrate contacting the heat dissipation plate in the third region. 
 
     
     
       8. The method of  claim 6 , further comprising, before the connecting of the second element:
 forming a third element on the second substrate; and 
 forming a second line connecting the conductive pads to the third element. 
 
     
     
       9. The method of  claim 8 , wherein the second element comprises a gallium nitride field effect transistor, and
 each of the first element and the third element comprises one selected from a capacitor, an inductor, and a resistor. 
 
     
     
       10. The method of  claim 1 , wherein the first element comprises a silicon field effect transistor, and
 the second element comprises a gallium nitride field effect transistor.