Graphene-based superconducting transistor

Abstract

A transistor. In some embodiments, the transistor includes a first superconducting source-drain, a second superconducting source-drain, a graphene channel including at least a portion of a graphene sheet, and a conductive gate. The first superconducting source-drain, the second superconducting source-drain, and the graphene channel together form a Josephson junction having a critical current. The graphene channel forms a current path between the first superconducting source-drain and the second superconducting source-drain. The conductive gate is configured, upon application of a electric field across the conductive gate and the graphene channel by applying a voltage, to modify the critical current.

What is claimed is: 
     
       1. A transistor comprising:
 a first superconducting source-drain, 
 a second superconducting source-drain, 
 a graphene channel comprising at least a portion of a graphene sheet, 
 a conductive gate, and 
 a gate insulating layer, 
 the first superconducting source-drain, the second superconducting source-drain, and the graphene channel together forming a Josephson junction having a critical current, 
 the graphene channel forming a current path between the first superconducting source-drain and the second superconducting source-drain, 
 the conductive gate being a conductive sheet on the graphene channel, between the first superconducting source-drain and the second superconducting source-drain, 
 the gate insulating layer being between the conductive gate and the graphene channel, and 
 the conductive gate being configured, upon application of a voltage across the conductive gate and the graphene channel, when each of the first superconducting source-drain and the second superconducting source-drain is in a superconducting state and the graphene channel is in a normal state, to modify the critical current. 
 
     
     
       2. The transistor of  claim 1 , further comprising a graphene sandwich comprising:
 a first layer of hexagonal boron nitride immediately adjacent a first surface of the graphene sheet, 
 the graphene sheet, and 
 a second layer of hexagonal boron nitride immediately adjacent a second surface of the graphene sheet. 
 
     
     
       3. The transistor of  claim 2 , wherein each of the first layer of hexagonal boron nitride and the second layer of hexagonal boron nitride has a thickness greater than 0.3 nm and less than 100 nm. 
     
     
       4. The transistor of  claim 2 , wherein the conductive gate is directly on the graphene sandwich. 
     
     
       5. The transistor of  claim 2 , wherein the gate insulating layer is directly on the graphene sandwich, and the conductive gate is directly on the gate insulating layer. 
     
     
       6. The transistor of  claim 5 , wherein the gate insulating layer is composed of aluminum oxide. 
     
     
       7. The transistor of  claim 2 , further comprising a substrate, the first superconducting source-drain, the second superconducting source-drain, and the graphene sandwich being on the substrate. 
     
     
       8. The transistor of  claim 7 , wherein the substrate is a silicon substrate. 
     
     
       9. The transistor of  claim 8 , wherein the substrate is a float zone crystalline silicon substrate. 
     
     
       10. The transistor of  claim 1 , wherein the graphene sheet has an electron mobility of more than 100,000 cm 2 /V/s. 
     
     
       11. The transistor of  claim 1 , wherein the graphene sheet substantially has the shape of a rectangle, the rectangle having a length and a width, the length being less than or equal to the width. 
     
     
       12. The transistor of  claim 11 , wherein the length of the rectangle is less than 0.5 microns and the width of the rectangle is greater than 0.5 microns. 
     
     
       13. The transistor of  claim 12 , wherein the length of the rectangle is between 0.1 microns and 0.3 microns, and the width of the rectangle is between 0.7 microns and 2.5 microns. 
     
     
       14. The transistor of  claim 1 , wherein the graphene sheet consists of a single atomic layer of graphene. 
     
     
       15. The transistor of  claim 1 , wherein the graphene sheet comprises two atomic layers of graphene. 
     
     
       16. The transistor of  claim 1 , wherein the first superconducting source-drain and the second superconducting source-drain are composed of a material selected from the group consisting of niobium nitride, niobium titanium nitride, niobium diselenide, aluminum, niobium, niobium titanium, and lead. 
     
     
       17. A system comprising the transistor of  claim 1 , and further comprising a refrigerator configured to cool the graphene sheet to a temperature below 4 K. 
     
     
       18. The system of  claim 17 , wherein the refrigerator is a pulse tube refrigerator.