Method for making three dimensional complementary metal oxide semiconductor carbon nanotube thin film transistor circuit

Abstract

A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

What is claimed is: 
     
       1. A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit, the method comprising:
 providing an insulating substrate; 
 applying a n-type carbon nanotube thin film transistor on the insulating substrate, wherein the n-type carbon nanotube thin film transistor comprises a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode; and 
 forming a p-type carbon nanotube thin film transistor on the insulating substrate, wherein the p-type carbon nanotube thin film transistor comprises a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode; the p-type carbon nanotube thin film transistor and the n-type carbon nanotube thin film transistor are stacked with each other; and 
 electrically connecting the first drain electrode and the second drain electrode; 
 wherein the n-type carbon nanotube thin film transistor is located between the p-type carbon nanotube thin film transistor and the insulating substrate; and the method for making the metal oxide semiconductor carbon nanotube thin film transistor circuit leaves a portion of the second semiconductor carbon nanotube layer between the second drain electrode and the second source electrode uncovered, whereby the portion of the second semiconductor carbon nanotube layer between the second drain electrode and the second source electrode is exposed and uncovered; and applying the n-type carbon nanotube thin film transistor on the insulating substrate comprises:
 treating the insulating substrate to form a polar surface; and 
 forming the first semiconductor carbon nanotube layer on the insulating substrate by applying a carbon nanotube suspension on the insulating substrate. 
 
 
     
     
       2. The method of  claim 1 , wherein both the p-type carbon nanotube thin film transistor and the n-type carbon nanotube thin film transistor is back gate type. 
     
     
       3. The method of  claim 2 , wherein the first gate electrode is located on the insulating substrate; the functional dielectric layer covers the first gate electrode; and the first semiconductor carbon nanotube layer, the first drain electrode and the first source electrode are located on the functional dielectric layer and spaced from the first gate electrode. 
     
     
       4. The method of  claim 3 , wherein the first insulating layer is located on and covers the first semiconductor carbon nanotube layer, the first drain electrode and the first source electrode; the second gate electrode is located on the first insulating layer; a second insulating layer is located on and covers the second gate electrode; the second semiconductor carbon nanotube layer, the second drain electrode and the second source electrode are located on the second insulating layer and spaced from the second gate electrode. 
     
     
       5. The method of  claim 1 , wherein the p-type carbon nanotube thin film transistor is back gate type and the n-type carbon nanotube thin film transistor is top gate type; and the first gate electrode and the second gate electrode are the same one gate electrode. 
     
     
       6. The method of  claim 5 , wherein the first semiconductor carbon nanotube layer, the first drain electrode, and the first source electrode are located on the insulating substrate; the functional dielectric layer covers the first semiconductor carbon nanotube layer, the first drain electrode, and the first source electrode; the first gate electrode is located on the functional dielectric layer and spaced from the first semiconductor carbon nanotube layer, the first drain electrode, and the first source electrode. 
     
     
       7. The method of  claim 6 , wherein the first insulating layer is located on the functional dielectric layer and covers the first gate electrode; the second semiconductor carbon nanotube layer, the second drain electrode, and the second source electrode are located on the first insulating layer. 
     
     
       8. The method of  claim 1 , wherein the insulating substrate is a polymer film. 
     
     
       9. The method of  claim 1 , wherein each of the first semiconductor carbon nanotube layer and the second semiconductor carbon nanotube layer comprises a plurality of single-walled carbon nanotubes connected with each other to form a conductive network. 
     
     
       10. The method of  claim 1 , wherein the functional dielectric layer comprises material selected from the group consisting of hafnium oxide, yttrium oxide, silicon nitride, magnesium oxide, potassium, and organic polymers. 
     
     
       11. The method of  claim 1 , wherein the functional dielectric layer comprises a magnesium oxide layer and an aluminum oxide layer. 
     
     
       12. The method of  claim 1 , wherein the functional dielectric layer comprises a silicon nitride layer and the first insulating layer comprises an aluminum oxide layer. 
     
     
       13. The method of  claim 1 , wherein the first insulating layer comprises a polymer film. 
     
     
       14. The method of  claim 1 , wherein the first drain electrode and the second drain electrode are electrically connected by making a through hole extending through at least on the first insulating layer. 
     
     
       15. The method of  claim 1 , wherein a method of treating the insulating substrate to form the polar surface comprises:
 hydrophilic treating the insulating substrate via ion etching; and 
 functionalizing the insulating substrate with an organic solution, so that a surface of the insulating substrate comprises a plurality of polar groups. 
 
     
     
       16. The method of  claim 1 , wherein the second drain electrode is in direct contact with the second semiconductor carbon nanotube layer, and the second source electrode is in direct contact with the second semiconductor carbon nanotube layer.