Electronic device including a high electron mobility transistor that includes a barrier layer having different portions

Abstract

An electronic device can include a HEMT that includes a channel layer, a barrier layer, and a gate electrode. The barrier layer can be disposed between the channel layer and the gate electrode and include a first portion, a second portion, and a third portion. The second portion can be spaced apart from the channel layer by the first portion, and the second portion is spaced apart from the gate electrode by the third portion. The second portion of the barrier layer can be configured to trap more charge, more readily recombine electrons and holes, or both as compared to each of the first and third portions of the barrier layer. The HEMT can have a VTH of at least 2 V and a subthreshold slope of at most 50 mV/decade of IDS.

What is claimed is: 
     
       1. An electronic device comprising a high electron mobility transistor comprising:
 a channel layer; 
 a first barrier layer including a first portion, a second portion, and a third portion; and 
 a gate electrode of the high electron mobility transistor, 
 wherein:
 the first barrier layer is disposed between the channel layer and the gate electrode, 
 the second portion of the first barrier layer is spaced apart from the channel layer by the first portion of the first barrier layer, 
 the second portion of the first barrier layer is spaced apart from the gate electrode by the third portion of the first barrier layer, 
 the second portion of the first barrier layer has a semiconductor base material different from a semiconductor base material of each of the first portion of the barrier layer and the third portion of the first barrier layer, and 
 the second portion of the first barrier layer is configured to trap more charge, more readily recombine electrons and holes, or both as compared to each of the first and third portions of the first barrier layer. 
 
 
     
     
       2. The electronic device of  claim 1 , wherein the second portion of the first barrier layer is configured to trap more charge and more readily recombine electrons and holes as compared to each of the first and third portions of the first barrier layer. 
     
     
       3. The electronic device of  claim 1 , wherein the first barrier layer further comprises a fourth portion and a fifth portion, wherein:
 the fourth portion of the first barrier layer is disposed between the third and fifth portions of the first barrier layer, 
 the fourth portion of the first barrier layer is spaced apart from the gate electrode by the fifth portion of the first barrier layer, and 
 the fourth portion of the first barrier layer is configured to trap more charge, more readily recombine electrons and holes, or both as compared to each of the third and fifth portions of the first barrier layer. 
 
     
     
       4. The electronic device of  claim 1 , wherein the second portion of the first barrier layer comprises a III-N material different from each of the first and third portions of the first barrier layer. 
     
     
       5. The electronic device of  claim 1 , wherein the second portion of the first barrier layer comprises In f Al g Ga (1-f-g) N, where 0<f≤1.0, 0≤g<1.0, and (f+g)≤1.0. 
     
     
       6. The electronic device of  claim 5 , wherein the first portion of the first barrier layer, the third portion of the first barrier layer, or both the first and third portions comprise Al z Ga (1-z) N, where 0.1≤z≤0.5. 
     
     
       7. The electronic device of  claim 1 , wherein the second portion has a higher crystal defect density as compared to each of the first and third portions of the first barrier layer. 
     
     
       8. The electronic device of  claim 1 , wherein the second portion of the first barrier layer has a thickness in a range from 1 nm to 30 nm. 
     
     
       9. The electronic device of  claim 1 , further comprising a gate interconnect, wherein the gate interconnect forms a Schottky contact with the gate electrode. 
     
     
       10. The electronic device of  claim 9 , wherein the gate electrode includes a p-type doped III-N material. 
     
     
       11. The electronic device of  claim 1 , wherein the high mobility electron transistor further comprises:
 a source electrode (1) overlying at least a portion of a first thickness of the first portion of the first barrier layer or a second barrier layer or (2) extending through the first portion of the first barrier layer or a second barrier layer and contacting the channel layer; and 
 a drain electrode (1) overlying at least a portion of a first thickness of the first portion of the first barrier layer or a second barrier layer or (2) extending through the first portion of the first barrier layer or a second barrier layer and contacting the channel layer. 
 
     
     
       12. The electronic device of  claim 11 , further comprising a gate interconnect, wherein:
 the channel layer includes GaN, 
 each of the first and third portions of the first barrier layer includes Al z Ga (1-z) N, where 0.1≤z≤0.5, 
 the second portion of the first barrier layer includes In f Al g Ga (1-f-g) N, where 0<f≤1.0, 0≤g<1.0, and (f+g)≤1.0, 
 the second portion of the first barrier layer is spaced apart from each of the channel layer and the gate electrode by at least 2 nm, 
 the gate electrode includes p-type GaN, and 
 the gate interconnect forms a Schottky contact with the gate electrode. 
 
     
     
       13. A method of using an electronic device comprising:
 coupling a drain electrode or a source electrode of a high electron mobility transistor to a first power supply, wherein the high electron mobility transistor further comprises:
 a gate electrode; 
 a channel layer underlying the source, drain, and gate electrodes; and 
 a barrier layer disposed between the channel layer and the gate electrode and including a first portion, a second portion, and a third portion, wherein the second portion is disposed between first and third portions, and the second portion has a higher In content, a higher dopant concentration, or a higher crystal defect density as compared to the first and third portions; 
 
 coupling the other of the drain electrode or the source electrode to an output node or a second power supply; and 
 increasing V GS  to turn on the transistor, wherein the transistor has a subthreshold slope of at most 50 mV/decade of I DS  over three decades of I DS . 
 
     
     
       14. The method of  claim 13 , wherein the transistor has a subthreshold slope of at most 30 mV/decade of I DS  over five decades of I DS . 
     
     
       15. The method of  claim 14 , further comprising decreasing V GS  to turn off the transistor, wherein the transistor has a turn-off slope of at least 50 mV/decade of I DS  over three decades of I DS . 
     
     
       16. The method of  claim 13 , wherein the high electron mobility transistor has a threshold voltage of at least 2.0 V. 
     
     
       17. The method of  claim 13 , wherein the high electron mobility transistor further comprises a gate interconnect that forms a Schottky contact with the gate electrode. 
     
     
       18. A process of forming an electronic device comprising a high electron mobility transistor, the process comprising:
 forming a barrier layer over a channel layer, wherein the barrier layer includes a first portion, a second portion, and a third portion, and the second portion is disposed between the first and third portions; 
 implanting ions into the barrier layer, such that after implanting is completed, the second portion has a higher dopant concentration or a higher crystal defect density as compared to each of the first and third portions; and 
 forming a gate electrode of the high electron mobility transistor over the barrier layer, 
 wherein:
 the second portion of the barrier layer is spaced apart from the channel layer by the first portion of the barrier layer, and 
 the second portion of the barrier layer is spaced apart from the gate electrode by the third portion of the barrier layer. 
 
 
     
     
       19. The process of  claim 18 , wherein in a finished electronic device, the second portion of the barrier layer has a higher crystal defect density as compared to each of the first portion of the barrier layer and the third portion of the barrier layer. 
     
     
       20. The process of  claim 18 , wherein implanting the ions into the barrier layer comprises implanting ions generated from a noble gas into the barrier layer.