Hybrid diamond solid-state circuit protector

Abstract

A solid-state circuit protector includes a first power semiconductor device having an ON resistance that increases with increasing temperature and a second power semiconductor device connected in parallel with the first power semiconductor device having an ON resistance that decreases with increasing temperature. During times when abnormally high currents are flowing through the solid-state circuit protector, the second power semiconductor is switched ON so that some or all of the current is diverted through it, thus protecting the first power semiconductor device from being damaged due to overheating. The first power semiconductor device is either switched OFF, allowing it to cool in anticipation of a lighter load, or is configured to remain ON so that it shares the burden of carrying the high current with the parallel-connected second power semiconductor device yet operates cooler and at a lower ON resistance since it is not required to pass the full current.

What is claimed is: 
     
       1. A solid-state circuit protector, comprising;
 a first power semiconductor device having an ON resistance that increases with increasing temperature; and 
 a second power semiconductor device connected in parallel with the first power semiconductor device having an ON resistance that decreases with increasing temperature, 
 wherein the second power semiconductor device comprises a power semiconductor device having a diamond semiconductor current path, a diamond semiconductor channel, or a diamond semiconductor base. 
 
     
     
       2. The solid-state circuit protector of  claim 1 , wherein the second power semiconductor device has a control terminal that allows it to be controlled to operate as a switch, and the solid-state circuit protector further comprises a controller that controls whether the second power semiconductor device is switched ON or is switched OFF. 
     
     
       3. The solid-state circuit protector of  claim 2 , wherein the controller is configured to:
 determine whether a current flowing through the first power semiconductor device is representative of a short circuit or imminent short circuit; and 
 switch the first power semiconductor OFF and the second power semiconductor ON temporarily for a short-circuit time-to-trip t SC , if it determines that the current flowing through the first power semiconductor device is representative of a short circuit or imminent short circuit. 
 
     
     
       4. The solid-state circuit protector of  claim 3 , wherein the controller is further configured to:
 determine whether a current flowing through the first power semiconductor device is representative of an overload; 
 switch the second power semiconductor ON, if the controller determines that the current flowing through the first power semiconductor device is representative of an overload; and 
 switch the second power semiconductor back OFF if the overload has persisted for an overload time-to-trip t OL . 
 
     
     
       5. The solid-state circuit protector of  claim 4 , wherein the controller is further configured to:
 determine whether a current flowing through the first power semiconductor device is representative of a heavy load; 
 switch the second power semiconductor ON, if the controller determines that the current flowing through the first power semiconductor device is representative of a heavy load; and 
 switch the second power semiconductor back OFF if the heavy load has persisted for a heavy load time-to-trip t HL . 
 
     
     
       6. The solid-state circuit protector of  claim 2 , further comprising a man-machine interface in electrical communication with the controller that provides an external computer and a user of the external computer the ability to define and set one or more trip-current settings for the solid-state circuit protector. 
     
     
       7. The solid-state circuit protector of  claim 6 , wherein the user-defined one or more trip-current settings include(s) a first current threshold, above which a short circuit condition is defined, and a short-circuit time-to-trip t SC . 
     
     
       8. The solid-state circuit protector of  claim 7 , wherein the user-defined one or more trip-current settings further include:
 a second current threshold, which along with the first current threshold define a range of overload currents, and 
 a range of overload times-to-trip corresponding to the range of overload currents. 
 
     
     
       9. The solid-state circuit protector of  claim 8 , wherein the user-defined one or more trip-current settings further include:
 a third current threshold, which along with the second current threshold define a range of heavy load currents, and 
 a range of heavy load times-to-trip corresponding to the range of heavy load currents. 
 
     
     
       10. The solid-state circuit protector of  claim 2 , wherein the first and second power semiconductor devices are configured to both remain ON during normal operating conditions and to also remain ON during short-circuit, overload, and heavy load conditions but only for durations dictated by predefined time-current characteristics of the solid-state circuit protector. 
     
     
       11. A circuit protection method, comprising:
 monitoring a current flowing through a solid-state device that includes a first power semiconductor device connected in parallel with a second power semiconductor device, the first power semiconductor device having an ON resistance that increases with increasing temperature and the second power semiconductor device having an ON resistance that decreases with increasing temperature; 
 determining whether the current exceeds a first current threshold representative of a short circuit or imminent short circuit; and 
 switching the first power semiconductor device OFF if the current is determined to exceed the first current threshold, 
 wherein the second power semiconductor device has a diamond semiconductor current path. 
 
     
     
       12. The circuit protection method of  claim 11 , wherein the second power semiconductor device comprises a field-effect transistor (FET) having a diamond semiconductor source-drain channel or comprises a bipolar transistor having a diamond semiconductor base. 
     
     
       13. The circuit protection method of  claim 11 , further comprising switching the second power semiconductor device OFF or maintaining the second power semiconductor device OFF, if already OFF, if the current is determined to exceed the first current threshold. 
     
     
       14. The circuit protection method of  claim 11 , further comprising:
 switching the second power semiconductor device ON temporarily, when the current is determined to exceed the first current threshold; and 
 switching the second power semiconductor device OFF after a short circuit time-to-trip t SC  has expired. 
 
     
     
       15. The circuit protection method of  claim 11 , further comprising:
 determining whether the current exceeds a second current threshold representative of an overload, if the current is determined not to exceed the first current threshold; 
 switching the first power semiconductor OFF and the second power semiconductor ON, if not already ON, if the current is determined to exceed the second current threshold and an overload is present; and 
 switching the second power semiconductor device OFF, if the overload has persisted for an overload time-to-trip t OL . 
 
     
     
       16. The circuit protection method of  claim 11 , further comprising:
 determining whether the current exceeds a second current threshold representative of an overload, if the current is determined not to exceed the first current threshold; 
 keeping the first power semiconductor device ON and switching the second power semiconductor ON, if not already ON, if the current is determined to exceed the second current threshold and an overload is present; and 
 switching the first and second power semiconductor devices OFF, if the overload has persisted for an overload time-to-trip t OL . 
 
     
     
       17. The circuit protection method of  claim 16 , further comprising:
 determining whether the current exceeds a third current threshold representative of a heavy load, if the current is determined not to exceed the second current threshold; 
 switching the first power semiconductor OFF and the second power semiconductor ON, if not already ON, if the current is determined to exceed the third current threshold and a heavy load is present; and 
 switching the second power semiconductor device OFF, if the heavy load has persisted for a heavy load time-to-trip t HL . 
 
     
     
       18. The circuit protection method of  claim 16 , further comprising:
 determining whether the current exceeds a third current threshold representative of a heavy load, if the current is determined not to exceed the second current threshold; 
 keeping the first power semiconductor device ON and switching the second power semiconductor ON, if not already ON, if the current is determined to exceed the third current threshold and a heavy load is present; and 
 switching the first and second power semiconductor devices OFF, if the heavy load has persisted for a heavy load time-to-trip t HL .