Data processing engine (DPE) array detailed mapping

Abstract

An example method for compiling by a processor-based system includes obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines; generating a global mapping of the program nodes based on a representation of the array of data processing engines; generating a detailed mapping of the program nodes based on the global mapping, the detailed mapping assigning input/outputs of programmable logic (PLIOs) of the device to channels in an interface of the array of data processing engines, the detailed mapping further assigning buffers of the application to individual memory banks in the array of data processing engines; and translating the detailed mapping to a file.

What is claimed is: 
     
       1. A method for compiling by a processor-based system, the method comprising:
 obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines; 
 generating a global mapping of the program nodes based on a representation of the array of data processing engines; 
 generating a detailed mapping of the program nodes based on the global mapping, the detailed mapping assigning incoming inputs and outputs of programmable logic (PLIOs) of the device to incoming channels of an interface of the array of data processing engines and assigning outgoing PLIOs of the device to outgoing channels of the interface of the array of data processing engines, the detailed mapping further assigning buffers of the application to individual memory banks in the array of data processing engines; and 
 translating the detailed mapping to a file. 
 
     
     
       2. The method of  claim 1 , wherein the detailed mapping further assigns offset values within each of the memory banks to the buffers. 
     
     
       3. The method of  claim 1 , wherein the detailed mapping is generated based on a plurality of constraints. 
     
     
       4. The method of  claim 3 , wherein the plurality of constraints includes assignment constraints, the assignment constraints specifying that:
 each incoming PLIO is to be placed at one incoming channel of the interface; 
 each outgoing PLIO is to be placed at one outgoing channel of the interface; and 
 each buffer ends at one of the memory banks. 
 
     
     
       5. The method of  claim 3 , wherein the plurality of constraints includes resource constraints, the resource constraints specifying that:
 each of the incoming channels has a maximum of one incoming PLIO; 
 each of the outgoing channels has a maximum of one outgoing PLIO; and 
 each of the memory banks does not include an overlapping pair of the buffers. 
 
     
     
       6. The method of  claim 3 , wherein the plurality of constraints includes relation constraints, the relation constraints specifying that ping-pong pairs of the buffers are not placed in the same one of the memory banks. 
     
     
       7. The method of  claim 3 , wherein the plurality of constraints includes optimization constraints, the optimization constraints specifying that only buffers larger than a memory bank are placed in more than one of the memory banks. 
     
     
       8. A non-transitory computer readable medium having instructions stored thereon that cause a processor to perform a method for compiling, the method comprising:
 obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines; 
 generating a global mapping of the program nodes based on a representation of the array of data processing engines; 
 generating a detailed mapping of the program nodes based on the global mapping, the detailed mapping assigning incoming inputs and outputs of programmable logic (PLIOs) of the device to incoming channels of an interface of the array of data processing engines and assigning outgoing PLIOs of the device to outgoing channels of the interface of the array of data processing engines, the detailed mapping further assigning buffers of the application to individual memory banks in the array of data processing engines; and 
 translating the detailed mapping to a file. 
 
     
     
       9. The non-transitory computer readable medium of  claim 8 , wherein the detailed mapping further assigns offset values within each of the memory banks to the buffers. 
     
     
       10. The non-transitory computer readable medium of  claim 8 , wherein the detailed mapping is generated based on a plurality of constraints. 
     
     
       11. The non-transitory computer readable medium of  claim 10 , wherein the plurality of constraints includes assignment constraints, the assignment constraints specifying that:
 each incoming PLIO is to be placed at one incoming channel of the interface; 
 each outgoing PLIO is to be placed at one outgoing channel of the interface; and 
 each buffer ends at one of the memory banks. 
 
     
     
       12. The non-transitory computer readable medium of  claim 10 , wherein the plurality of constraints includes resource constraints, the resource constraints specifying that:
 each of the incoming channels has a maximum of one incoming PLIO; 
 each of the outgoing channels has a maximum of one outgoing PLIO; and 
 each of the memory banks does not include an overlapping pair of the buffers. 
 
     
     
       13. The non-transitory computer readable medium of  claim 10 , wherein the plurality of constraints includes relation constraints, the relation constraints specifying that ping-pong pairs of the buffers are not placed in the same one of the memory banks. 
     
     
       14. The non-transitory computer readable medium of  claim 10 , wherein the plurality of constraints includes optimization constraints, the optimization constraints specifying that only buffers larger than a memory bank are placed in more than one of the memory banks. 
     
     
       15. A design system comprising:
 a processor; and 
 a memory coupled to the processor, the memory storing instruction code, the processor being configured to execute the instruction code to perform:
 obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines; 
 generating a global mapping of the program nodes based on a representation of the array of data processing engines; 
 generating a detailed mapping of the program nodes based on the global mapping, the detailed mapping assigning incoming inputs and outputs of programmable logic (PLIOs) of the device to incoming channels of an interface of the array of data processing engines and assigning outgoing PLIOs of the device to outgoing channels of the interface of the array of data processing engines, the detailed mapping further assigning buffers of the application to individual memory banks in the array of data processing engines; and 
 translating the detailed mapping to a file. 
 
 
     
     
       16. The design system of  claim 15 , wherein the detailed mapping further assigns offset values within each of the memory banks to the buffers. 
     
     
       17. The design system of  claim 15 , wherein the detailed mapping is generated based on a plurality of constraints. 
     
     
       18. The design system of  claim 17 , wherein the plurality of constraints includes assignment constraints, the assignment constraints specifying that:
 each incoming PLIO is to be placed at one incoming channel of the interface; 
 each outgoing PLIO is to be placed at one outgoing channel of the interface; and 
 each buffer ends at one of the memory banks. 
 
     
     
       19. The design system of  claim 18 , wherein the plurality of constraints includes resource constraints, the resource constraints specifying that:
 each of the incoming channels has a maximum of one incoming PLIO; 
 each of the outgoing channels has a maximum of one outgoing PLIO; and 
 each of the memory banks does not include an overlapping pair of the buffers. 
 
     
     
       20. The design system of  claim 18 , wherein the plurality of constraints includes relation constraints, the relation constraints specifying that ping-pong pairs of the buffers are not placed in the same one of the memory banks.