Ultra high density thin film transistor substrate having low line resistance structure and method for manufacturing the same

Abstract

A display device is described that has reduced resistance in one or more of the gate, common, data electrical lines that control the operation of the pixels of the display device. Reduced resistance is achieved by forming additional metal and/or metal-alloy layers on the gate, common, and/or data lines in such a manner so that the cross-sectional area of those lines is increased. As a consequence, each such line is formed so as to be thicker than could otherwise be achieving without causing defects in the rubbing process of an alignment layer. Additionally, no widening of these lines is needed, thus preserving the aspect ratio of the device. The gate insulating and semiconducting layers that in part make up the thin film transistors that help control the operation of the pixels of the device may also be designed to take into account the increased thickness of the lines.

What is claimed is: 
     
       1. A display device comprising:
 a substrate having a first area, and a second area outside of the first area, the second area including a link area and a pad area outside of the link area; 
 gate lines and data lines crossing each other, and thin film transistors adjacent to crossings of the gate lines and the data lines in the first area, each of the thin film transistors including a source electrode, a semiconductor channel layer and a drain electrode; 
 a first line extended from each of the gate lines and an additional gate line formed of a same material as the data lines in the link area, the additional gate line being contacted with the first line in the link area; and 
 a gate pad extended from each of the first lines and a gate pad terminal on the gate pad, in the pad area, wherein at least a portion of the additional gate line directly contacts at least a portion of a top surface of a semiconductor layer formed of a same material as the semiconductor channel layer. 
 
     
     
       2. The display device of  claim 1 , further comprising;
 an additional data line positioned on a same layer as the gate line to be separated from the gate line; 
 a data pad extended from the additional data line, in the pad area; and 
 a data pad terminal on the data pad, in the pad area. 
 
     
     
       3. The display device of  claim 2 , wherein the gate pad terminal and the data pad terminal are formed of a same material. 
     
     
       4. The display device of  claim 1 , further comprising the semiconductor layer on a gate insulating layer covering the first line in the pad area, wherein the additional gate line is connected to a surface of the first line and a side of at least one of the first line and the semiconductor layer. 
     
     
       5. The display device of  claim 4 , further comprising a common line, and an additional data line positioned on a same layer as the gate line to be separated from the gate line. 
     
     
       6. The display device of  claim 5 , further comprising an additional common line on the common line in the first area, wherein the data line, the additional gate line, and the additional common line are formed of a same data material. 
     
     
       7. The display device of  claim 6 , wherein at a point where the common line and the data line cross each other, the gate insulating layer is formed and the semiconductor layer is not formed. 
     
     
       8. The display device of  claim 6 , wherein the gate insulating layer and the semiconductor layer are both formed at a point where the gate line and the data line cross each other. 
     
     
       9. The display device of  claim 6 , wherein the gate insulating layer is formed on a portion of the additional data line, the additional common line is in contact with a portion of the common line not covered by the gate insulating layer, and the data line is formed on a portion of the gate insulating layer formed on a portion of the additional data line. 
     
     
       10. The display device of  claim 1 , wherein the gate line and the data line are formed of a stacked structure comprising multiple metal layers, multiple alloy layers, or multiple layers including at least one metal layer and at least one alloy layer. 
     
     
       11. The display device of  claim 10 , wherein the stacked structure comprises a layer of molybdenum-titanium alloy and a layer of copper or aluminum. 
     
     
       12. The display device of  claim 2 , wherein the additional data line is formed in a plurality of segments along the data line, and wherein one of the segments is disposed between the gate line and an adjacent gate line or between the gate line and a common line. 
     
     
       13. The display device of  claim 1 , wherein a majority of a bottom surface of the additional gate line is in physical contact with a majority of a top surface of the gate line. 
     
     
       14. The display device of  claim 2 , wherein a majority of a bottom surface of the additional data line is in physical contact with a majority of a top surface of the data line. 
     
     
       15. The display device of  claim 2 , wherein the gate insulating layer covers less than a majority of the gate line, and the additional data line. 
     
     
       16. The display device of  claim 1 , wherein the additional gate line is positioned on the gate line not covered by a gate insulating layer covering the gate line, the data line and the gate electrode in the first area.