US10840897B1ActiveUtility

Noise canceling technique for a sine to square wave converter

93
Assignee: SILICON LAB INCPriority: Oct 31, 2019Filed: Oct 31, 2019Granted: Nov 17, 2020
Est. expiryOct 31, 2039(~13.3 yrs left)· nominal 20-yr term from priority
H03K 5/05H03L 7/1976H03L 7/08H03K 5/1565H03B 5/32H03L 7/099H03B 28/00H03L 7/0896
93
PatentIndex Score
12
Cited by
32
References
20
Claims

Abstract

A sine to square wave converter circuit receives a sine wave signal and supplies a first square wave signal having a first frequency. A 2× clock multiplier circuit multiplies the first square wave signal and supplies a second square wave signal with a second frequency that is twice the first frequency. A first storage element that is clocked by the second square wave signal stores a delayed version of the first square wave signal and supplies an even-odd signal. A second storage element that is clocked by the second square wave signal receives the even-odd signal and supplies an odd-even signal. A duty cycle correction circuit adjusts the threshold of the sine to square wave converter based on a difference in duty pulse widths between the even-odd signal and the odd-even signal.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. An apparatus comprising:
 a sine to square wave converter circuit coupled to receive a sine wave signal and supply a first square wave signal having a first frequency; 
 a clock multiplier circuit coupled to receive the first square wave signal and to supply a second square wave signal having a second frequency; 
 a duty cycle correction circuit coupled to the sine to square wave converter circuit to adjust a threshold of the sine to square wave converter circuit based on a difference in pulse widths between a first signal having the first frequency and a second signal having the first frequency; 
 a first storage element having an input coupled to the first square wave signal, the first storage element clocked by the second square wave signal supplied by the clock multiplier circuit, the first storage element supplying an even-odd signal as the first signal; and 
 a second storage element having an input coupled to the even-odd signal, the second storage element clocked by the second square wave signal and the second storage element supplying an odd-even signal as the second signal. 
 
     
     
       2. The apparatus as recited in  claim 1 , wherein the first storage element is coupled to the first square wave signal through a delay circuit. 
     
     
       3. The apparatus as recited in  claim 1 , wherein the duty cycle correction circuit comprises:
 a charge pump responsive to supply a current reflecting the difference in pulse widths between the odd-even signal and even-odd signal; and 
 an operational amplifier coupled between the charge pump and an input to the sine to square wave converter circuit. 
 
     
     
       4. The apparatus as recited in  claim 3 , wherein the charge pump is a differential charge pump. 
     
     
       5. The apparatus as recited in  claim 4 , further comprising:
 a first resistor and a first capacitor coupled in series between a first input of the operational amplifier and a first output of the operational amplifier; and 
 a second resistor and a second capacitor coupled in series between a second input of the operational amplifier and a second output of the operational amplifier. 
 
     
     
       6. The apparatus as recited in  claim 3 , further comprising:
 a bias resistor coupled between an output of the operational amplifier and the input to the sine to square wave converter circuit. 
 
     
     
       7. An apparatus comprising:
 a sine to square wave converter circuit coupled to receive a sine wave signal and supply a first square wave signal having a first frequency; 
 a clock multiplier circuit coupled to receive the first square wave signal and to supply a second square wave signal having a second frequency that is twice the first frequency; 
 a duty cycle correction circuit coupled to supply a voltage to an input of the sine to square wave converter circuit to adjust a threshold of the sine to square wave converter circuit based on a difference in pulse widths between a first signal having the first frequency and a second signal having the first frequency; and 
 a startup circuit configured to cause the duty cycle correction circuit to adjust the threshold of the sine to square wave converter circuit only after a peak amplitude of the sine wave signal is above a threshold voltage. 
 
     
     
       8. The apparatus as recited in  claim 7 , wherein the startup circuit further comprises:
 a peak detector circuit to compare the peak amplitude of the sine wave signal to the threshold voltage and to supply a peak detect signal indicative thereof; and 
 a first switch to couple an output of the duty cycle correction circuit to the sine to square wave converter circuit responsive to the peak detect signal indicating the peak amplitude of the sine wave signal is above the threshold voltage and to decouple the output of the duty cycle correction circuit from the sine to square wave converter circuit responsive to the peak detect signal indicating the peak amplitude of the sine wave signal is not above the threshold voltage. 
 
     
     
       9. The apparatus as recited in  claim 8 , wherein the startup circuit further comprises:
 a second switch to couple a fixed voltage to the sine to square wave converter circuit responsive to the peak detect signal indicating the peak amplitude of the sine wave signal is not above the threshold voltage and to decouple the fixed voltage from the sine to square wave converter circuit responsive to the peak detect signal indicating the peak amplitude of the sine wave signal is above the threshold voltage. 
 
     
     
       10. The apparatus as recited in  claim 1 , further comprising:
 a phase-locked loop coupled to receive the second square wave signal as a reference signal. 
 
     
     
       11. The apparatus as recited in  claim 1 , further comprising:
 a crystal oscillator coupled to supply the sine wave signal to the sine to square wave converter circuit. 
 
     
     
       12. A method as comprising:
 converting a sine wave signal to a first square wave signal having a first frequency in a sine to square wave converter circuit; 
 multiplying the first square wave signal in a clock multiplier circuit and supplying a second square wave signal having a second frequency that is twice the first frequency; 
 generating a first signal with the first frequency and a second signal with the first frequency; 
 adjusting a threshold of the sine to square wave converter circuit based on a difference in pulse widths between the first signal and the second signal; 
 supplying a delayed version of the first square wave signal to a first storage element; 
 clocking the first storage element with the second square wave signal and supplying an even-odd signal from the first storage element as the first signal; and 
 supplying the even-odd signal to a second storage element; and 
 clocking the second storage element with the second square wave signal and supplying an odd-even signal from the second storage element as the second signal. 
 
     
     
       13. The method as recited in  claim 12 , further comprising:
 generating a current reflecting a difference in pulse widths between opposite polarities of the odd-even signal and even-odd signal; 
 supplying an operational amplifier having an integrating capacitor with the current; and 
 adjusting a threshold of the sine to square wave converter circuit based on an output of the operational amplifier. 
 
     
     
       14. The method as recited in  claim 13 , further comprising:
 preventing the adjusting of the threshold of the sine to square wave converter circuit based on the difference in duty cycle between the even-odd signal and the odd-even signal until after a peak amplitude of the sine wave signal is above a threshold voltage. 
 
     
     
       15. The method as recited in  claim 14 , further comprising:
 comparing the peak amplitude of the sine wave signal to the threshold voltage and supplying a peak detect signal indicative thereof; 
 coupling the output of the operational amplifier to the sine to square wave converter circuit through a first switch responsive to the peak detect signal indicating the peak amplitude of the sine wave signal is above the threshold voltage; and 
 keeping the output of the operational amplifier from being coupled to the sine to square wave converter circuit through the first switch responsive to the peak detect signal indicating the peak amplitude of the sine wave signal is not above the threshold voltage. 
 
     
     
       16. The method as recited in  claim 15 , further comprising:
 coupling a fixed voltage to the sine to square wave converter circuit through a second switch responsive to the peak detect signal indicating the peak amplitude of the sine wave signal is not above the threshold voltage; and 
 preventing the fixed voltage from being coupled to the sine to square wave converter circuit through the second switch responsive to the peak detect signal indicating the peak amplitude of the sine wave signal is above the threshold voltage. 
 
     
     
       17. The method as recited in  claim 12 , further comprising:
 generating the sine wave signal in a crystal oscillator; 
 supplying the sine wave signal to the sine to square wave converter circuit; and 
 supplying the second square wave signal as a reference signal to a phase-locked loop. 
 
     
     
       18. An apparatus comprising:
 a sine to square wave converter circuit coupled to receive a sine wave signal and supply a first square wave signal having a first frequency; 
 a clock multiplier circuit coupled to receive the first square wave signal and to supply a second square wave signal having a second frequency that is twice the first frequency; 
 a first storage element having an input coupled to a delayed version of the first square wave signal, the first storage element clocked by the second square wave signal supplied by the clock multiplier circuit, and the first storage element supplying an even-odd signal; 
 a second storage element having an input coupled to the even-odd signal, the second storage element clocked by the second square wave signal and the second storage element supplying an odd-even signal; and 
 a duty cycle correction circuit coupled to supply a voltage to an input of the sine to square wave converter circuit to adjust a conversion threshold of the sine to square wave converter circuit based on a difference in pulse widths between the even-odd signal and the odd-even signal. 
 
     
     
       19. The apparatus as recited in  claim 1  wherein the second frequency is twice the first frequency. 
     
     
       20. The apparatus as recited in  claim 1  wherein the duty cycle correction circuit is coupled to supply a voltage to an input of the sine to square wave converter circuit to adjust the threshold of the sine to square wave converter circuit.

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