High-side gate driver for gallium nitride integrated circuits

Abstract

A gate driver circuit for a gallium nitride (GaN) power transistor includes a RS-flipflop that receives a first pulse train at an S input terminal and a second pulse train at an R input terminal, and produces an output pulse train, and an amplifier that amplifies the output pulse train and produces a gate driver signal for the GaN power transistor. The RS-flipflop and the amplifier may be implemented together on a GaN monolithic integrated circuit, optionally together with the GaN power transistor. The GaN power transistor may be a high-side switch of a half-bridge circuit. The RS-flipflop may be implemented with enhancement mode and depletion mode GaN high electron mobility transistors (HEMTs). Embodiments avoid drawbacks of prior hybrid (e.g., silicon-GaN) approaches, such as parasitic inductances from bonding wires and on-board metal traces, especially at high operating frequencies, as well as reduce implementation cost and improve performance.

The invention claimed is: 
     
       1. A gate driver circuit for a gallium nitride (GaN) power transistor, comprising:
 a RS-flipflop that receives a first pulse train at an S input terminal and a second pulse train at an R input terminal, and produces an output pulse train; 
 a direct-coupled FET logic (DCFL) amplifier that amplifies the output pulse train and produces a gate driver signal for the GaN power transistor; 
 wherein the first pulse train and the second pulse train are independently controlled signals; 
 wherein the DCFL amplifier comprises: 
 a first stage input point, a first stage output point, a second stage high side input point, a second stage low side input point, and an amplifier output point; 
 wherein the first stage input point is connected to a first stage and to the second stage high side input point; and 
 wherein the first stage output point is connected to the second stage low side input point. 
 
     
     
       2. The gate driver circuit of  claim 1 , wherein the RS-flipflop is implemented on a GaN monolithic integrated circuit;
 wherein the RS-flipflop comprises: 
 four EHEMTs and two DHEMTs; 
 wherein a first two of the EHEMTs are of a large channel width and are arranged back-to-back as main RS-flipflop transistors; 
 wherein a second two of the EHEMTs are of a small channel width and are arranged as R and S input transistors; 
 wherein the two DHEMTs are configured as non-linear loads for the main RS-flipflop transistors. 
 
     
     
       3. The gate driver circuit of  claim 2 , wherein a ratio of transistor channel widths for the two EHEMTs of a large channel width, the two EHEMTs of a small channel width, and the two DHEMTs is (100±50):(30±15):(1±0.5), respectively. 
     
     
       4. The gate driver circuit of  claim 2 , further comprising a device that outputs the first pulse train and the second pulse train;
 wherein a pulse width of the first pulse train is within a range of about 5 ns to 15 ns; and 
 wherein a pulse width of the second pulse train is within a range of about 5 ns to 15 ns. 
 
     
     
       5. The gate driver circuit of  claim 4 , further comprising a first transformer that couples the first pulse train to the S input terminal of the RS-flipflop; and
 a second transformer that couples the second pulse train to the R input terminal of the RS-flipflop. 
 
     
     
       6. The gate driver circuit of  claim 5 , wherein magnetizing inductance ratios for the first transformer and for the second transformer are about (7±3.5) μH:(7±3.5) μH for a 10 ns pulse width. 
     
     
       7. A method for implementing a gate driver circuit for a GaN power transistor, comprising:
 using a RS-flipflop to receive a first pulse train at an S input terminal, receive a second pulse train at an R input terminal, and produce an output pulse train; 
 amplifying the output pulse train to produce a gate driver signal for the GaN power transistor; 
 wherein the first pulse train and the second pulse train are independently controlled signals; 
 the method further comprising implementing the RS-flipflop on a GaN monolithic integrated circuit; 
 wherein the RS-flipflop comprises: 
 four EHEMTs and two DHEMTs; 
 wherein a first two of the EHEMTs are of a large channel width and are arranged back-to-back as main RS-flipflop transistors; 
 wherein a second two of the EHEMTs are of a small channel width and are arranged as R and S input transistors; 
 wherein the two DHEMTs are configured as non-linear loads for the main RS-flipflop transistors. 
 
     
     
       8. The method of  claim 7 , wherein a ratio of transistor channel widths for the two EHEMTs of a large channel width, the two EHEMTs of a small channel width, and the two DHEMTs is (100±50):(30±15):(1±0.5), respectively.