Clamp logic circuit

Abstract

A clamp logic circuit has a logic circuit, a control terminal, a current clamp circuit and an output terminal. The logic circuit has at least a junction field-effect transistor (JFET). The control terminal receives an input signal. The current clamp circuit has a transistor and a resistor. A first end of the transistor is coupled to the control terminal, a second end of the transistor is coupled to a first end of the resistor, a control end of the transistor is coupled to a reference voltage, and a second end of the resistor is coupled to an input end of the logic circuit. The output terminal is coupled to an output end of the logic circuit.

What is claimed is: 
     
       1. A clamp logic circuit, comprising:
 a logic circuit, comprising at least a junction field-effect transistor (JFET); 
 a control terminal, configured to receive an input signal; 
 a current clamp circuit, configured to limit a maximum of a current flowing from the control terminal into the current clamp circuit to be less than a predetermined value when an external alternating current (AC) signal is transmitted to the control terminal, the current clamp circuit comprising a first transistor and a first resistor, a first end of the first transistor being coupled to the control terminal, a second end of the first transistor being coupled to a first end of the first resistor, a control end of the first transistor being coupled to a reference voltage, and a second end of the first resistor being coupled to an input end of the logic circuit; and 
 an output terminal, coupled to an output end of the logic circuit. 
 
     
     
       2. The clamp logic circuit of  claim 1 , wherein the current clamp circuit further comprises a high impedance network coupled between the control end of the first transistor and the reference voltage, and the high impedance network comprises a resistor, a transistor or an inductor. 
     
     
       3. The clamp logic circuit of  claim 1 , wherein the logic circuit comprises an inverter. 
     
     
       4. The clamp logic circuit of  claim 1 , wherein the at least a JFET comprises a plurality of JFETs, and the plurality of JFETs are a plurality of pseudomorphic high-electron-mobility transistors (pHEMTs). 
     
     
       5. The clamp logic circuit of  claim 1 , wherein the first transistor is a depletion-mode (D-mode) field-effect transistor (FET). 
     
     
       6. The clamp logic circuit of  claim 2  further comprising a first capacitor, a first end of the first capacitor being coupled to the input end of the logic circuit and the second end of the first resistor, a second end of the first capacitor being coupled to the reference voltage, and the first capacitor and the first resistor forming a low pass filter. 
     
     
       7. The clamp logic circuit of  claim 3 , wherein the at least a JFET comprises an enhancement-mode (E-mode) field-effect transistor (FET) and a depletion-mode (D-mode) field-effect transistor (FET). 
     
     
       8. The clamp logic circuit of  claim 6  further comprising a direct current (DC) offset circuit coupled between the control terminal and the first end of the first transistor. 
     
     
       9. The clamp logic circuit of  claim 8 , wherein the DC offset circuit comprises a first rectifying device, a first end of the first rectifying device is coupled to the control terminal, and a second end of the first rectifying device is coupled to the first end of the first transistor. 
     
     
       10. The clamp logic circuit of  claim 8  further comprising a low pass filter coupled between the control terminal and the DC offset circuit. 
     
     
       11. The clamp logic circuit of  claim 9 , wherein the first rectifying device comprises a diode-connected transistor, a first end and a control end of the diode-connected transistor are coupled to each other and are coupled to the control terminal, and a second end of the diode-connected transistor is coupled to the first end of the first transistor. 
     
     
       12. The clamp logic circuit of  claim 9 , wherein the first rectifying device comprises a first diode, a first end of the first diode is coupled to the control terminal, and a second end of the first diode is coupled to the first end of the first transistor. 
     
     
       13. The clamp logic circuit of  claim 9  further comprising a second rectifying device, a first end of the second rectifying device being coupled to the second end of the first rectifying device, and a second end of the second rectifying device being coupled to the first end of the first rectifying device, wherein the second rectifying device and the first rectifying device provide a bi-directional conducting path between the control terminal of the clamp logic circuit and the first end of the first transistor. 
     
     
       14. The clamp logic circuit of  claim 11  further comprising at least one of a first high pass filter, a second high pass filter and a third high pass filter, wherein the first high pass filter is coupled between the first end of the first transistor and the second end of the first transistor, the second high pass filter is coupled between the first end of the diode-connected transistor and the second end of the diode-connected transistor, and the third high pass filter is coupled between the control end of the first transistor and the control end of the diode-connected transistor. 
     
     
       15. The clamp logic circuit of  claim 11  further comprising at least one of a first high pass filter and a second high pass filter, wherein the first high pass filter is coupled between the control terminal of the clamp logic circuit and the second end of the first transistor, and the second high pass filter is coupled between the control end of the first transistor and the control end of the diode-connected transistor. 
     
     
       16. The clamp logic circuit of  claim 12  further comprising a second rectifying device, wherein the second rectifying device comprises a second diode, a first end of the second diode is coupled to the second end of the first diode, and a second end of the second diode is coupled to the first end of the first diode. 
     
     
       17. The clamp logic circuit of  claim 13  further comprising a first high pass filter, wherein the first high pass filter is coupled between the control end of the first transistor and the second end of the first rectifying device. 
     
     
       18. The clamp logic circuit of  claim 14 , wherein the first high pass filter comprises a second capacitor, the second high pass filter comprises a third capacitor or the third high pass filter comprises a fourth capacitor. 
     
     
       19. The clamp logic circuit of  claim 15 , wherein the first high pass filter comprises a second capacitor or the second high pass filter comprises a third capacitor. 
     
     
       20. The clamp logic circuit of  claim 17 , wherein the first high pass filter comprises a second capacitor.