Attenuating common mode noise current in current mirror circuits

Abstract

At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.

What is claimed is: 
     
       1. A circuit comprising:
 a voltage supply line; a capacitor coupled to the voltage supply line; 
 a first current mirror component coupled to the voltage supply line, wherein the capacitor and the first current mirror component are arranged in a parallel connection; 
 a second current mirror component coupled to the voltage supply line; a current source coupled to a reference voltage; and 
 mirrored circuitry including a first terminal and a second terminal, wherein the capacitor and a first terminal of the first current mirror component are coupled in common to the first terminal of the mirrored circuitry, and wherein a second terminal of the first current mirror component, the second current mirror component, and the current source are coupled in common to the second terminal of the mirrored circuitry. 
 
     
     
       2. The circuit of  claim 1 , comprising:
 additional circuitry having a first terminal coupled to the second current mirror component and a second terminal coupled to the reference voltage, wherein the mirrored circuitry replicates at least a portion of the additional circuitry. 
 
     
     
       3. The circuit of  claim 1 , wherein:
 the first current mirror component includes a first transistor; and 
 the second current mirror component includes a second transistor. 
 
     
     
       4. The circuit of  claim 3 , wherein the first and second transistors have different sizes. 
     
     
       5. The circuit of  claim 4 , wherein the second transistor has a larger size than the first transistor. 
     
     
       6. The circuit of  claim 3 , wherein a sizing ratio of the first transistor to the second transistor is 1 to N, wherein N>1. 
     
     
       7. The circuit of  claim 3 , wherein a gate of the first transistor and a gate of the second transistor are coupled in common to the second terminal of the mirror circuitry, the gate of the first transistor being the second terminal of the first current mirror component. 
     
     
       8. The circuit of  claim 1 , wherein the mirrored circuitry is arranged between the first current mirror component and the current source. 
     
     
       9. The circuit of  claim 8 , wherein the mirror circuitry includes:
 a first transistor having a source terminal and a drain terminal; and 
 a second transistor having a source terminal and a drain terminal; 
 wherein the first and second transistors are arranged in a parallel connection so that the source terminal of the first transistor and the source terminal of the second transistor are coupled in common to the first terminal of the mirrored circuitry and the drain terminal of the first transistor and the drain terminal of the second transistor are coupled in common to the second terminal of the mirrored circuitry. 
 
     
     
       10. The circuit of  claim 9 , wherein the first current mirror component includes a third transistor having a source terminal coupled to the voltage supply line, a drain terminal coupled to each of the source terminal of the first transistor and the source terminal of the second transistor, and a gate terminal coupled to each of the drain terminal of the first transistor and the drain terminal of the second transistor, wherein the drain terminal of the third transistor is the first terminal of the first current mirror component. 
     
     
       11. The circuit of  claim 10 , wherein the second current mirror component includes a fourth transistor having a source terminal coupled to the voltage supply line and a gate terminal coupled to each of the drain terminal of the first transistor, the drain terminal of the second transistor, and the gate terminal of the third transistor. 
     
     
       12. The circuit of  claim 1 , wherein the second current mirror component includes a first transistor having a source terminal coupled to the voltage supply line and a gate terminal coupled to the current source. 
     
     
       13. The circuit of  claim 12 , comprising additional circuitry arranged between the reference voltage and the second current mirror component, wherein the mirrored circuitry replicates at least a portion of the additional circuitry. 
     
     
       14. The circuit of  claim 13 , wherein the additional circuitry includes a first terminal and a second terminal, wherein the first transistor includes a drain terminal coupled to the first terminal of the additional circuitry and the second terminal of the additional circuitry is coupled to the reference voltage. 
     
     
       15. A circuit comprising:
 a supply voltage; 
 a reference voltage; 
 a current mirror circuit including a first transistor having a source terminal coupled to the supply voltage and a second transistor having a source terminal coupled to the supply voltage; 
 mirrored circuitry having a first terminal coupled in series to a drain terminal of the first transistor at a first node; 
 a current source having a first terminal coupled in series to a second terminal of the mirrored circuitry at a second node and a second terminal coupled to the reference voltage, wherein the mirrored circuitry is arranged between the first transistor and the current source, wherein a gate terminal of the first transistor and a gate terminal of the second transistor are coupled in common to the second node; and 
 a capacitor having a first terminal coupled to the supply voltage and a second terminal coupled to the first node. 
 
     
     
       16. The circuit of  claim 15 , comprising additional circuitry having a first terminal coupled in series to a drain terminal of the second transistor at a third node and a second terminal coupled to the reference voltage. 
     
     
       17. The circuit of  claim 15 , wherein the mirrored circuitry includes a third transistor and a fourth transistor, wherein the third and fourth transistors are arranged in a parallel connection with a source terminal of the third transistor and a source terminal of the fourth transistor coupled to the first node and a drain terminal of the third transistor and a drain terminal of the fourth transistor coupled to the second node. 
     
     
       18. A circuit comprising:
 a supply voltage; a reference voltage; 
 a current mirror circuit including a first transistor having a source terminal coupled to the supply voltage; 
 mirrored circuitry having a first terminal coupled in series to a drain terminal of the first transistor at a first node; 
 a current source having a first terminal coupled in series to a second terminal of the mirrored circuitry at a second node and a second terminal coupled to the reference voltage, wherein the mirrored circuitry is arranged between the first transistor and the current source; and 
 a capacitor having a first terminal coupled to the supply voltage and a second terminal coupled to the first node; 
 wherein the mirrored circuitry includes a third transistor and a fourth transistor, wherein the third and fourth transistors are arranged in a parallel connection with a source terminal of the third transistor and a source terminal of the fourth transistor coupled to the first node and a drain terminal of the third transistor and a drain terminal of the fourth transistor coupled to the second node.