Self-test of an asynchronous circuit

Abstract

An indication of an operating mode of an asynchronous circuit may be received. A determination may be made as to whether the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit. In response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, a first clock signal may be provided to a first portion of a self-test component in a feedback path of the asynchronous circuit and a second clock signal may be provided to a second portion of the self-test component in the feedback path of the asynchronous circuit. Furthermore, a test value may be generated based on the first clock signal and the second clock signal.

What is claimed is: 
     
       1. A method comprising:
 receiving, by a first circuit, an indication of an operating mode of an asynchronous circuit; 
 determining, by the first circuit, that the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit; 
 in response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, providing, by the first circuit, a first clock signal to a first portion of a second circuit in a feedback path of the asynchronous circuit and a second clock signal to a second portion of the second circuit in the feedback path of the asynchronous circuit; and 
 generating, by the asynchronous circuit, a test value based on the first clock signal and the second clock signal. 
 
     
     
       2. The method of  claim 1 , wherein the first portion of the second circuit is a first latch and the second portion of the second circuit is a second latch. 
     
     
       3. The method of  claim 2 , further comprising:
 determining that the operating mode of the asynchronous circuit does not correspond to the self-test; and 
 in response to determining that the operating mode of the asynchronous circuit does not correspond to the self-test:
 providing a first signal to the first latch of the second circuit in the feedback path of the asynchronous circuit and a second signal to the second latch of the second circuit, the first signal to enable the first latch and the second signal to not enable the second latch, the second latch being transparent when it is not enabled; and 
 generating, by the asynchronous circuit, a value that is used in a cryptographic operation based on the first signal and the second signal. 
 
 
     
     
       4. The method of  claim 1 , wherein the asynchronous circuit is a random number generator to generate one or more random values that are used in a cryptographic operation. 
     
     
       5. The method of  claim 1 , wherein the providing of the first clock signal and the second clock signal changes the asynchronous circuit from a deterministic behavior to a non-deterministic behavior. 
     
     
       6. The method of  claim 1 , wherein the indication of the operating mode of the asynchronous circuit is based on a condition of the asynchronous circuit, the method further comprising:
 determining a number of values that have been generated by the asynchronous circuit when the operating mode of the asynchronous circuit does not correspond to the self-test, wherein the indication is received when the number of values that have been generated by the asynchronous circuit exceeds a threshold number. 
 
     
     
       7. The method of  claim 1 , wherein the indication of the operating mode of the asynchronous circuit is based on a condition of the asynchronous circuit, the method further comprising:
 identifying a type of cryptographic operation that is to be performed with a value from the asynchronous circuit, the indication being received based on the type of cryptographic operation that is to be performed with the value from the asynchronous circuit. 
 
     
     
       8. An integrated circuit comprising:
 an asynchronous circuit comprising a self-test circuit in a feedback path of the asynchronous circuit; and 
 a controller circuit, operatively coupled with the asynchronous circuit, to:
 receive an indication of an operating mode of the asynchronous circuit; 
 determine that the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit; and 
 in response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, provide a first clock signal to a first portion of the self-test circuit in the feedback path of the asynchronous circuit and a second clock signal to a second portion of the self-test circuit in the feedback path of the asynchronous circuit, wherein the asynchronous circuit generates a test value based on the first clock signal and the second clock signal. 
 
 
     
     
       9. The integrated circuit of  claim 8 , wherein the first portion of the self-test circuit is a first latch and the second portion of the self-test circuit is a second latch. 
     
     
       10. The integrated circuit of  claim 9 , wherein the controller circuit is further to:
 determine that the operating mode of the asynchronous circuit does not correspond to the self-test; and 
 in response to determining that the operating mode of the asynchronous circuit does not correspond to the self-test:
 provide a first signal to the first latch of the self-test circuit in the feedback path of the asynchronous circuit and a second signal to the second latch of the self-test circuit, the first signal to enable the first latch and the second signal to not enable the second latch, the second latch being transparent when it is not enabled, and wherein the asynchronous circuit generates a value that is used in a cryptographic operation based on the first signal and the second signal. 
 
 
     
     
       11. The integrated circuit of  claim 8 , wherein the asynchronous circuit is a random number generator to generate one or more random values that are used in a cryptographic operation. 
     
     
       12. The integrated circuit of  claim 8 , wherein the providing of the first clock signal and the second clock signal changes the asynchronous circuit from a non-deterministic behavior to a deterministic behavior. 
     
     
       13. The integrated circuit of  claim 8 , wherein the indication of the operating mode of the asynchronous circuit is based on a condition of the asynchronous circuit, the controller circuit is further to:
 determine a number of values that have been generated by the asynchronous circuit when the operating mode of the asynchronous circuit does not correspond to the self-test, wherein the indication is received when the number of values that have been generated by the asynchronous circuit exceeds a threshold number. 
 
     
     
       14. The integrated circuit of  claim 8 , wherein the indication of the operating mode of the asynchronous circuit is based on a condition of the asynchronous circuit, the controller circuit is further to:
 identify a type of cryptographic operation that is to be performed with a value from the asynchronous circuit, the indication being received based on the type of cryptographic operation that is to be performed with the value from the asynchronous circuit. 
 
     
     
       15. A system comprising:
 a memory; and 
 a processing device, operatively coupled with the memory, the processing device comprising a first circuit, a self-test circuit, and an asynchronous circuit, the processing device to:
 receive, by the first circuit, an indication of an operating mode of the asynchronous circuit; 
 determine, by the first circuit that the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit; 
 in response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, provide, by the first circuit, a first clock signal to a first portion of the self-test circuit in a feedback path of the asynchronous circuit and a second clock signal to a second portion of the self-test circuit in the feedback path of the asynchronous circuit; and 
 generate, by the asynchronous circuit, a test value based on the first clock signal and the second clock signal. 
 
 
     
     
       16. The system of  claim 15 , wherein the first portion of the self-test circuit is a first latch and the second portion of the self-test circuit is a second latch. 
     
     
       17. The system of  claim 16 , wherein the processing device is further to:
 determine that the operating mode of the asynchronous circuit does not correspond to the self-test; and 
 in response to determining that the operating mode of the asynchronous circuit does not correspond to the self-test:
 provide a first signal to the first latch of the self-test circuit in the feedback path of the asynchronous circuit and a second signal to the second latch of the self-test circuit, the first signal to enable the first latch and the second signal to not enable the second latch, the second latch being transparent when it is not enabled; and 
 generate, by the asynchronous circuit, a value that is used in a cryptographic operation based on the first signal and the second signal. 
 
 
     
     
       18. The system of  claim 15 , wherein the asynchronous circuit is a random number generator to generate one or more random values that are used in a cryptographic operation. 
     
     
       19. The system of  claim 15 , wherein the providing of the first clock signal and the second clock signal changes the asynchronous circuit from a non-deterministic behavior to a deterministic behavior. 
     
     
       20. The system of  claim 15 , wherein the indication of the operating mode of the asynchronous circuit is based on a condition of the asynchronous circuit, the processing device is further to:
 determine a number of values that have been generated by the asynchronous circuit when the operating mode of the asynchronous circuit does not correspond to the self-test, wherein the indication is received when the number of values that have been generated by the asynchronous circuit exceeds a threshold number.