Time to digital converter and A/D conversion circuit

Abstract

A time to digital converter includes a state transition section configured to start, based on a trigger signal, state transition in which an internal state transitions, a transition-state acquiring section configured to acquire, in synchronization with a reference signal, state information from the state transition section and hold the state information, and an arithmetic operation section configured to calculate, based on the state information, a time digital value corresponding to the number of times of transition of the internal state. The state transition section includes a tapped delay line to which a plurality of delay elements are coupled, a logic circuit, and a state machine. The state information is represented by count information output from the state machine and propagation information output from the tapped delay line. A hamming distance of the state information before and after the state transition is 1. A time from when the internal state transitions from a first internal state to a second internal state until when the internal state reverts to the first internal state is longer than a time interval for updating the state information held by the transition-state acquiring section.

What is claimed is: 
     
       1. A time to digital converter to which a reference signal and a trigger signal are input, the time to digital converter outputting a time digital value corresponding to a time event of the trigger signal, the time to digital converter comprising:
 a state transition section configured to output state information indicating an internal state and start, based on the trigger signal, state transition in which the internal state transitions; 
 a transition-state acquiring section configured to acquire, in synchronization with the reference signal, the state information from the state transition section and hold the state information; and 
 an arithmetic operation section configured to calculate, based on the state information, the time digital value corresponding to a number of times of transition of the internal state, wherein 
 the state transition section includes a tapped delay line to which a plurality of delay elements are coupled, a logic circuit, and a state machine, 
 the state information is represented by count information output from the state machine and propagation information output from the tapped delay line, 
 a hamming distance of the state information before and after the state transition is 1, and 
 a time from when the internal state transitions from a first internal state to a second internal state until when the internal state reverts to the first internal state is longer than a time interval for updating the state information held by the transition-state acquiring section. 
 
     
     
       2. The time to digital converter according to  claim 1 , wherein the state transition section stops the state transition when the number of times of transition exceeds a number of times based on an upper limit value. 
     
     
       3. The time to digital converter according to  claim 1 , wherein the arithmetic operation section calculates a number of times of state transition based on the state information, weights the number of times of state transition based on elapse of time, and integrates the weighted number of times of state transition to calculate and output the time digital value. 
     
     
       4. The time to digital converter according to  claim 3 , wherein the arithmetic operation section corrects the number of times of state transition using a delay amount of each of the plurality of delay elements. 
     
     
       5. The time to digital converter according to  claim 1 , wherein
 a plurality of the trigger signals are input, and 
 the arithmetic operation section generates the time digital value from a difference between a first time digital value corresponding to a time event of a first trigger signal among the plurality of trigger signals and a second time digital value corresponding to a time event of a second trigger signal among the plurality of trigger signals. 
 
     
     
       6. An A/D conversion circuit that converts an input analog signal into a digital signal and outputs the digital signal, the A/D conversion circuit comprising:
 the time to digital converter according to  claim 1 ; 
 a reference-waveform-signal generation circuit configured to generate a reference waveform signal based on the reference signal; and 
 a comparator configured to compare a voltage of the analog signal and a voltage of the reference waveform signal and output the trigger signal, wherein 
 the A/D conversion circuit outputs the digital signal based on the time digital value generated by the time to digital converter. 
 
     
     
       7. An A/D conversion circuit that converts an input analog signal into a digital signal and outputs the digital signal, the A/D conversion circuit comprising:
 the time to digital converter according to  claim 1 ; 
 a sample hold circuit configured to sample and hold a voltage of the analog signal; 
 a reference-waveform-signal generation circuit configured to generate a reference waveform signal based on the reference signal; and 
 a comparator configured to compare the voltage held by the sample hold circuit and a voltage of the reference waveform signal and output the trigger signal, wherein 
 the A/D conversion circuit outputs the digital signal based on the time digital value generated by the time to digital converter.