Array substrate and display panel

Abstract

An array substrate may include a display area and a non-display area surrounding the display area. The display area may include at least one antistatic wiring; and a plurality of scan lines. The at least one antistatic wiring may be configured to conduct static electricity, and the at least one antistatic wiring and the plurality of scan lines may be interlaced and insulated. The at least one antistatic wiring may include a first wiring portion and a second wiring portion adjacent to each other. The first wiring portion and the second wiring portion may be located in different layers.

What is claimed is: 
     
       1. An array substrate comprising a display area and a non-display area surrounding the display area, and the display area comprising:
 at least one antistatic wiring; and 
 a plurality of scan lines; 
 wherein the at least one antistatic wiring is configured to conduct static electricity, and the at least one antistatic wiring and the plurality of scan lines are interlaced and insulated; 
 the at least one antistatic wiring comprises an first wiring portion and a second wiring portion adjacent to each other, and the first wiring portion and the second wiring portion are located in different layers; 
 the first wiring portion is interlaced with the plurality of scan lines, the second wiring portion is located on both sides of the plurality of scan lines, and/or the at least one antistatic wiring is located in a position in the display area near the non-display area; 
 the display area further comprises a first functional layer, a second functional layer, a signal line layer, and a second metal layer sequentially arranged on the array substrate, and the second functional layer is configured to form a thin film transistor; 
 the first functional layer comprises the first wiring portion; the second metal layer comprises the second wiring portion; a first through hole is defined on the second functional layer; the second wiring portion passes through the second functional layer via the first through hole to be connected to the first wiring portion. 
 
     
     
       2. The array substrate according to  claim 1 , wherein
 the display area further comprises a first functional layer, a second functional layer, a signal line layer, and a second metal layer sequentially arranged on the array substrate, and the second functional layer is configured to form a thin film transistor; 
 the first functional layer comprises the first wiring portion; the second metal layer comprises the second wiring portion; a first through hole is defined on the second functional layer; the second wiring portion passes through the second functional layer via the first through hole to be connected to the first wiring portion. 
 
     
     
       3. The array substrate according to  claim 2 , wherein
 the second functional layer comprises a buffer layer, a semiconductor layer, and a first insulating layer arranged stackedly; 
 the signal line layer comprises a first metal layer and a second insulating layer arranged stackedly; the first metal layer comprises the plurality of scan lines and a gate electrode of the thin film transistor, and the second metal layer further comprises a source electrode of thin film transistor and a drain electrode of thin film transistor. 
 
     
     
       4. The array substrate according to  claim 3 , wherein
 the second insulating layer comprises a first region arranged on the second insulating layer; a second through hole is defined on the first region; and the second wiring portion passes through the second insulating layer via the second through hole and passes through the second functional layer via the first through hole to be connected to the first wiring portion. 
 
     
     
       5. The array substrate according to  claim 4 , wherein
 the second metal layer further comprises a plurality of data lines; a third through hole is defined on the first region of the second insulating layer and defined on the first insulating layer; the source electrode and the drain electrode pass through the second insulating layer and pass through the first insulating layer via the third through hole to connected to the semiconductor layer. 
 
     
     
       6. The array substrate according to  claim 4 , wherein
 the first insulating layer comprises a second region arranged on the buffer layer; a first sub-through hole is defined on the second region, and a second sub-through hole corresponding to the first sub-through hole is defined on the buffer layer; the first sub-through hole and the second sub-through hole cooperatively are defined to the first through hole; a diameter of the second through hole is greater than or equal to a diameter of the first sub-through hole, and the diameter of the first sub-through hole is greater than or equal to a diameter of the second sub-through hole. 
 
     
     
       7. The array substrate according to  claim 2 , wherein
 the first functional layer further comprises a light blocking portion corresponding to a portion that the thin film transistor arranged. 
 
     
     
       8. The array substrate according to  claim 7 , wherein
 the light blocking portion and the first wiring portion are formed by an etching process with a same mask. 
 
     
     
       9. An array substrate comprising a display area and a non-display area surrounding the display area, and the display area comprising:
 at least one antistatic wiring; and 
 a plurality of scan lines; 
 wherein the at least one antistatic wiring is configured to conduct static electricity, and the at least one antistatic wiring and the plurality of scan lines are interlaced and insulated; 
 the at least one antistatic wiring comprises a first wiring portion and a second wiring portion adjacent to each other, and the first wiring portion and the second wiring portion are located in different layers; 
 wherein the display area further comprises a first functional layer, a second functional layer, a signal line layer, and a second metal layer sequentially arranged on the array substrate, and the second functional layer is configured to form a thin film transistor; 
 the first functional layer comprises the first wiring portion; the second metal layer comprises the second wiring portion; a first through hole is defined on the second functional layer; the second wiring portion passes through the second functional layer via the first through hole to be connected to the first wiring portion. 
 
     
     
       10. The array substrate according to  claim 9 , wherein
 the first wiring portion is interlaced with the plurality of scan lines, the second wiring portion is located on both sides of the plurality of scan lines, and/or 
 the at least one antistatic wiring is located in a position at an edge of the display area. 
 
     
     
       11. A display panel comprising an array substrate; the array substrate comprising a display area and a non-display area surrounding the display area, and the display area comprising:
 at least one antistatic wiring; and 
 a plurality of scan lines; 
 wherein the at least one antistatic wiring is configured to conduct static electricity, and the at least one antistatic wiring and the plurality of scan lines are interlaced and insulated; 
 the at least one antistatic wiring comprises a first wiring portion and a second wiring portion adjacent to each other, and the first wiring portion and the second wiring portion are located in different layers; 
 wherein the display area further comprises a first functional layer, a second functional layer, a signal line layer, and a second metal layer sequentially arranged on the array substrate, and the second functional layer is configured to form a thin film transistor; 
 the first functional layer comprises the first wiring portion; the second metal layer comprises the second wiring portion; a first through hole is defined on the second functional layer; the second wiring portion passes through the second functional layer via the first through hole to be connected to the first wiring portion. 
 
     
     
       12. The display panel according to  claim 11 , wherein
 the first wiring portion is interlaced with the plurality of scan lines, the second wiring portion is located on both sides of the plurality of scan lines, and/or 
 the at least one antistatic wiring is located in a position at an edge of the display area. 
 
     
     
       13. The array substrate according to  claim 11 , wherein
 the second functional layer comprises a buffer layer, a semiconductor layer, and a first insulating layer arranged stackedly; 
 the signal line layer comprises a first metal layer and a second insulating layer arranged stackedly; the first metal layer comprises the plurality of scan lines and a gate electrode of the thin film transistor, and the second metal layer further comprises a source electrode of thin film transistor and a drain electrode of thin film transistor. 
 
     
     
       14. The array substrate according to  claim 13 , wherein
 the second insulating layer comprises a first region arranged on the second insulating layer; a second through hole is defined on the first region; and the second wiring portion passes through the second insulating layer via the second through hole and passes through the second functional layer via the first through hole to be connected to the first wiring portion. 
 
     
     
       15. The array substrate according to  claim 14 , wherein
 the second metal layer further comprises a plurality of data lines; a third through hole is defined on the first region of the second insulating layer and defined on the first insulating layer; the source electrode and the drain electrode pass through the second insulating layer and pass through the first insulating layer via the third through hole to connected to the semiconductor layer. 
 
     
     
       16. The array substrate according to  claim 14 , wherein
 the first insulating layer comprises a second region arranged on the buffer layer; a first sub-through hole is defined on the second region, and a second sub-through hole corresponding to the first sub-through hole is defined on the buffer layer; the first sub-through hole and the second sub-through hole cooperatively are defined to the first through hole; a diameter of the second through hole is greater than or equal to a diameter of the first sub-through hole, and the diameter of the first sub-through hole is greater than or equal to a diameter of the second sub-through hole. 
 
     
     
       17. The array substrate according to  claim 11 , wherein
 the first functional layer further comprises a light blocking portion corresponding to a portion that the thin film transistor arranged. 
 
     
     
       18. The array substrate according to  claim 17 , wherein
 the light blocking portion and the first wiring portion are formed by an etching process with a same mask.