Overvoltage detection circuit with first and longer second response times

Abstract

A light emitting diode system allows for high current end user LED matrix applications while mitigating internal damage to control circuitry that may be caused by excess current flow. In one example, multiple switches operate in parallel across an LED. When an overvoltage condition is detected in a first switch, a logic circuit determines those switches programmed to operate in parallel and causes them to conduct current. This reduces the amount of current flowing through any one switch and mitigates harm to the device. The parallel configuration of switches may be driven by a single pulse width modulated current. This allows the drive current to be divided between parallel transistors, limiting the damaging effects that can be caused by high currents flowing through the transistors.

What is claimed is: 
     
       1. A circuit comprising:
 first and second terminals; 
 an overvoltage detection circuit coupled to the first and second terminals, and configured to generate an overvoltage signal upon detecting a voltage across the first and second terminals above a predetermined threshold voltage; 
 a first signal path configured to enable a current path across the first and second terminals within a first response time triggered by the overvoltage signal; and 
 a second signal path configured to enable the current path across the first and second terminals within a second response time triggered by either the overvoltage signal or an external fault detection signal received from an external circuit, wherein the second response time is greater than the first response time. 
 
     
     
       2. The circuit of  claim 1 , wherein the first signal path includes:
 a voltage supply terminal; and 
 a switch having a first end coupled to the voltage supply terminal, and a second end coupled to the current path, the switch configured to couple the first end to the second end in response to the overvoltage signal. 
 
     
     
       3. The circuit of  claim 1 , wherein:
 the current path includes an NMOS transistor having a drain coupled to the first terminal, a source coupled to the second terminal, and a gate; and 
 the first signal path includes:
 an inverter having an input coupled to receive the overvoltage signal, and an output; and 
 a PMOS transistor having a source coupled to a voltage supply terminal, a drain coupled to the gate of the NMOS transistor, and a gate coupled to the output of the inverter. 
 
 
     
     
       4. The circuit of  claim 1 , wherein:
 the current path includes an NMOS transistor having a drain coupled to the first terminal, a source coupled to the second terminal, and a gate; and 
 the second signal path includes an OR gate having a first input configured to receive the overvoltage signal, a second input configured to receive the external fault detection signal, and an output coupled to the gate of the NMOS transistor. 
 
     
     
       5. The circuit of  claim 1 , wherein:
 the current path includes an NMOS transistor having a drain coupled to the first terminal, a source coupled to the second terminal, and a gate; and 
 the second signal path includes: 
 a latch having a set input configured to receive the overvoltage signal, a reset input configured to receive the external fault detection signal, and a latch output; 
 an OR gate having a first input coupled to the latch output, a second input configured to receive the external fault detection signal, and an output; and 
 a driver having a driver input coupled to the output of the OR gate, and a driver output coupled to the gate of the NMOS transistor. 
 
     
     
       6. The circuit of  claim 5 , wherein the latch includes an inverted latch output configured to generate an internal fault detection signal for enabling an external circuit path of the external circuit. 
     
     
       7. The circuit of  claim 1 , wherein the overvoltage detection circuit includes a comparator having a first input coupled to the first terminal, a second input coupled to receive the predetermined threshold voltage, and an output configured to deliver the overvoltage signal. 
     
     
       8. The circuit of  claim 1 , wherein the second signal path is configured to generate an internal fault detection signal based on the overvoltage signal, the internal fault detection signal is configured to enable an external circuit path of the external circuit. 
     
     
       9. The circuit of  claim 1 , further comprising:
 an electronic device having a positive terminal coupled to the first terminal, and a negative terminal coupled to the second terminal, wherein the current path is configured to short-circuit the electronic device when enabled by at least one of the first signal path or the second signal path. 
 
     
     
       10. The circuit of  claim 1 , further comprising:
 an light emitting diode (LED) having an anode coupled to the first terminal, and a cathode coupled to the second terminal, wherein the current path is configured to short-circuit the LED when enabled by at least one of the first signal path or the second signal path. 
 
     
     
       11. A circuit comprising:
 first and second terminals; 
 a first switch coupled between the first and second terminals, and having a first control; 
 an overvoltage detection circuit configured to assert an overvoltage signal upon detecting a voltage across the first and second terminals above a predetermined threshold voltage; 
 a second switch having a second control responsive to the overvoltage signal, and configured to enable the first control within a first response time after the overvoltage signal is asserted; and 
 a logic circuit configured to enable the first control within a second response time after the overvoltage signal is asserted or after an external fault detection signal is received from an external circuit, wherein the second response time is greater than the first response time. 
 
     
     
       12. The circuit of  claim 11 , wherein the overvoltage detection circuit includes a comparator having a first input coupled to the first terminal, a second input coupled to receive the predetermined threshold voltage, and an output configured to deliver the overvoltage signal. 
     
     
       13. The circuit of  claim 11 , wherein the logic circuit is configured to generate an internal fault detection signal based on the overvoltage signal, the internal fault detection signal is configured to enable an external circuit path of the external circuit. 
     
     
       14. The circuit of  claim 11 , wherein:
 the first switch includes an NMOS transistor having a drain coupled to the first terminal, a source coupled to the second terminal, and a gate; and 
 the second switch includes a PMOS transistor having a source coupled to a voltage supply terminal, a drain coupled to the gate of the NMOS transistor, and a gate coupled to receive an inverted version of the overvoltage signal. 
 
     
     
       15. The circuit of  claim 11 , wherein:
 the first switch includes an NMOS transistor having a drain coupled to the first terminal, a source coupled to the second terminal, and a gate; and 
 the logic circuit includes:
 a latch having a set input configured to receive the overvoltage signal, a reset input configured to receive the external fault detection signal, and a latch output; 
 an OR gate having a first input coupled to the latch output, a second input configured to receive the external fault detection signal, and an output; and 
 a driver having a driver input coupled to the output of the OR gate, and a driver output coupled to the gate of the NMOS transistor. 
 
 
     
     
       16. An integrated circuit comprising:
 (a) first and second terminals adapted to be coupled to a light emitting diode; 
 (b) a light emitting diode switch coupled between the first and second terminals and having a gate terminal; 
 (c) a gate driver circuit having a driver input and having a driver output coupled to the gate terminal; 
 (d) a latch circuit having an over voltage input and a latch output coupled to the driver input, the latch circuit has a second input and a second output; 
 (e) an over voltage comparator having a first input coupled to the first terminal, having a threshold voltage input, and having a comparator output coupled to the over voltage input; 
 (f) fault register output circuitry having an input coupled to the latch second output; and 
 (g) driver input circuitry having an output coupled to the latch second input and the driver input. 
 
     
     
       17. The integrated circuit of  claim 16  including gating circuitry having a first input coupled to the latch output, a register input, and a gated output coupled to the driver input. 
     
     
       18. The integrated circuit of  claim 16  including an over voltage switch having a terminal coupled to the gate terminal and a gate terminal coupled to the comparator output. 
     
     
       19. The integrated circuit of  claim 16  including:
 a gate circuit having a first input, a second input, and an output coupled to the driver input; 
 a fault register output circuit having an input; and 
 a driver input circuit having an output coupled to the gate circuit second input; and 
 in which the latch circuit is a set and reset latch having a set input coupled to the comparator output, having a reset input coupled to the driver input circuit output, having an inverting output coupled to the fault register output circuit input, and having a non-inverting output coupled to the gate circuit first input.