Variable resistance memory devices

Abstract

A variable resistance memory device includes a memory unit including a first electrode, a variable resistance pattern and a second electrode sequentially stacked on a substrate, a first selection structure on the memory unit, a third electrode structure on the first selection structure, and an anti-fuse including a fourth electrode, a second selection structure and a fifth electrode structure sequentially stacked. The fourth electrode directly contacts the second selection structure, and a bottom of the fourth electrode is lower than a bottom of the second electrode.

What is claimed is: 
     
       1. A variable resistance memory device, comprising:
 a memory unit comprising a first electrode, a variable resistance pattern, and a second electrode, the first electrode, the variable resistance pattern, and the second electrode being sequentially stacked on a substrate; 
 a first selection structure disposed on the memory unit for selection via a word line or a bit line of the variable resistance memory device; 
 a third electrode structure disposed on the first selection structure; and 
 an anti-fuse comprising a fourth electrode, a second selection structure for selection via the word line or the bit line of the variable resistance memory device, and a fifth electrode structure sequentially stacked, 
 wherein the memory unit and the anti-fuse are formed in a cell region of the variable resistance memory device. 
 
     
     
       2. The variable resistance memory device of  claim 1 , wherein a bottom surface of the fourth electrode is substantially coplanar with a bottom surface of the first electrode. 
     
     
       3. The variable resistance memory device of  claim 1 , wherein the fourth electrode directly contacts the first electrode. 
     
     
       4. The variable resistance memory device of  claim 1 , wherein the fourth electrode is comprised of a material substantially the same as a material of the first electrode. 
     
     
       5. The variable resistance memory device of  claim 1 , wherein an uppermost surface of the fourth electrode is higher than an uppermost surface of the first electrode. 
     
     
       6. The variable resistance memory device of  claim 1 , wherein a length of the fourth electrode in a vertical direction substantially perpendicular to an upper surface of the substrate is greater than a length of the first electrode in the vertical direction. 
     
     
       7. The variable resistance memory device of  claim 1 , wherein a cross-section of the first electrode has a U-shape in a direction substantially perpendicular to an upper surface of the substrate, and
 wherein the variable resistance pattern and the second electrode are stacked on each of uppermost surfaces of the first electrode. 
 
     
     
       8. The variable resistance memory device of  claim 1 , wherein a cross-section of the fourth electrode in a direction substantially perpendicular to an upper surface of the substrate has a U-shape, and
 wherein the second selection structure and the fifth electrode structure are stacked on each of uppermost surfaces of the fourth electrode. 
 
     
     
       9. The variable resistance memory device of  claim 1 , wherein a length of the fourth electrode in a vertical direction substantially perpendicular to an upper surface of the substrate is substantially equal to a length of the memory unit in the vertical direction. 
     
     
       10. The variable resistance memory device of  claim 1 , wherein a thickness of the fourth electrode is substantially equal to a thickness of the first electrode. 
     
     
       11. The variable resistance memory device of  claim 1 , wherein each of the first selection structure and the second selection structure includes a first buffer, a selection pattern and a second buffer sequentially stacked. 
     
     
       12. The variable resistance memory device of  claim 1 , further comprising:
 first conductive lines disposed in a second direction substantially parallel to an upper surface of the substrate, each of the first conductive lines extending in a first direction substantially parallel to the upper surface of the substrate, the second direction crossing the first direction; and 
 second conductive lines disposed in the first direction over the first conductive lines, each of the second conductive lines extending in the second direction, 
 wherein the memory unit is formed at each of first regions among regions between the first and second conductive lines, the regions being regions at which the first and second conductive lines overlap with each other in a third direction substantially perpendicular to the upper surface of the substrate, and 
 wherein the anti-fuse is formed at a second region among the regions. 
 
     
     
       13. The variable resistance memory device of  claim 1 , wherein the fourth electrode directly contacts the second selection structure, and a bottom surface of the fourth electrode is lower than a bottom surface of the second electrode. 
     
     
       14. The variable resistance memory device of  claim 5 , wherein the uppermost surface of the fourth electrode is substantially coplanar with an upper surface of the second electrode. 
     
     
       15. The variable resistance memory device of  claim 7 , wherein the uppermost surface of the first electrode directly contacts a bottom surface of the variable resistance pattern and has an area smaller than an area of the bottom surface of the variable resistance pattern. 
     
     
       16. The variable resistance memory device of  claim 11 , wherein the selection pattern includes an ovonic threshold switch (OTS) material containing germanium (Ge), silicon (Si), arsenic (As) and tellurium (Te). 
     
     
       17. The variable resistance memory device of  claim 12 , wherein the regions are disposed in each of the first and second directions, and a plurality of second regions is disposed in one of the first and second directions, and
 the anti-fuse is formed at each of the plurality of second regions. 
 
     
     
       18. A variable resistance memory device, comprising:
 first conductive lines disposed on a substrate in a second direction parallel to an upper surface of the substrate, each of the first conductive lines extending in a first direction substantially parallel to the upper surface of the substrate, the second direction crossing the first direction; 
 second conductive lines disposed in the first direction over the first conductive lines, each of the second conductive lines extending in the second direction; 
 memory units at first regions, respectively, among regions between the first and second conductive lines, the regions being regions at which the first and second conductive lines overlap with each other in a third direction substantially perpendicular to the upper surface of the substrate, and each of the memory units including a first electrode, a variable resistance pattern, and a second electrode sequentially stacked; 
 a first selection structure disposed on each of the memory units for selection via a word line or a bit line of the variable resistance memory device; 
 a third electrode structure on the first selection structure; and 
 an anti-fuse at a second region among the regions, the anti-fuse comprising a fourth electrode, a second selection structure for selection via the word line or the bit line of the variable resistance memory device, and a fifth electrode structure sequentially stacked, 
 wherein a length of the fourth electrode in the third direction is greater than a length of the first electrode in the third direction. 
 
     
     
       19. The variable resistance memory device of  claim 18 , wherein a bottom surface of the fourth electrode is substantially coplanar with a bottom surface of the first electrode, and an uppermost surface of the fourth electrode is substantially coplanar with an upper surface of the second electrode. 
     
     
       20. The variable resistance memory device of  claim 18 , wherein the second selection structure directly contacts the fourth electrode.