Apparatus having on-chip fail safe logic for I/O signal in high integrity functional safety applications

Abstract

A packaged integrated circuit (IC) chip that provides input/output (I/O) signal fail safe verification is disclosed. The packaged IC chip includes a first processing unit, a first control peripheral coupled to receive a first processed signal from the processing unit and to provide an output signal, and compare logic. The compare logic is coupled to receive the output signal and a comparison signal, to compare the output signal and the comparison signal, and to provide an error signal responsive to a difference between the output signal and the comparison signal.

What is claimed is: 
     
       1. An integrated circuit (IC), the IC comprising:
 a first processing unit having a first process signal output; 
 a first control unit having a first control unit input and a first control unit output, the first control unit input is coupled to the first process signal output; 
 a redundant control unit having a redundant control unit input and a redundant control unit output, the redundant control unit input is coupled to the first process signal output; 
 a multiplexer having a multiplexer input and a multiplexer output, the multiplexer input is coupled to the redundant control unit output; and 
 a comparator having a first input coupled to the first control unit output, a comparison signal input, and an error signal output, the comparison signal input is coupled to the multiplexer output. 
 
     
     
       2. The IC in  claim 1  further comprising:
 a first processing chain that comprises a first sense converter, the first processing unit and the first control unit, the first sense converter being coupled to receive a first input signal and to provide a first digital signal to the first processing unit; and 
 a second processing chain comprising a second sense converter, a second processing unit and a second control unit, the second sense converter being coupled to receive a second input signal and to provide a second digital signal to the second processing unit, the second control unit being coupled to receive a second processed signal from the second processing unit and to provide a redundant processing chain signal to the multiplexer for selective use as a comparison signal. 
 
     
     
       3. The IC in  claim 2  further comprising:
 a first bond pad coupled to receive an output signal and to provide the output signal to a first device pin; and 
 a second bond pad coupled to receive an input signal from a second device pin and to provide the input signal to the multiplexer for selective use as the comparison signal. 
 
     
     
       4. The IC in  claim 3  wherein the multiplexer is further coupled to receive an external test signal for selective use as the comparison signal. 
     
     
       5. The IC in  claim 2  further comprising:
 a first bond pad coupled to receive an output signal and to provide the output signal to a first device pin; and 
 a second bond pad coupled to receive an input signal from a first device package pin and to provide the input signal to the multiplexer for selective use as the comparison signal. 
 
     
     
       6. The IC in  claim 1  wherein the first control unit receives a first processed signal, the redundant control unit receives a third processed signal, the first processed signal is provided by a first algorithm running on the first processing unit, and the third processed signal is provided by a second algorithm running on the first processing unit. 
     
     
       7. The IC in  claim 1  wherein the first control unit is a pulse width modulator. 
     
     
       8. The IC in  claim 1  wherein the comparator is a smart comparator. 
     
     
       9. The IC in  claim 1  wherein the comparator comprises an exclusive OR logic gate. 
     
     
       10. The IC in  claim 1  further comprising a redundant processing chain that is coupled to the comparison signal input. 
     
     
       11. The IC in  claim 1  further comprising a device package pin that is coupled to the comparison signal input.