Analog-to-digital converter device and method for calibrating clock skew

Abstract

An analog-to-digital converter (ADC) device includes ADC circuitries, a calibration circuitry, and a skew adjusting circuitry. The ADC circuitries convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuitry performs at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuitry analyzes time difference information within even-numbered sampling periods of the clock signals, in order to generate adjustment signals. The adjustment signals are for reducing a clock skew in the ADC circuitries.

What is claimed is: 
     
       1. An analog-to-digital converter device, comprising:
 a plurality of analog-to-digital converter circuitries configured to convert an input signal according to an interleaved plurality of clock signals to generate a plurality of first quantized outputs; 
 a calibration circuitry configured to perform at least one calibration operation according to the first quantized outputs to generate a plurality of second quantized outputs; and 
 a skew adjusting circuitry configured to analyze a time difference information within even-numbered sampling periods of the clock signals according to the second quantized outputs, so as to generate a plurality of adjustment signals, wherein the adjustment signals are for reducing a clock skew in the analog-to-digital converter circuitries, and the skew adjusting circuitry comprises:
 a first adjusting circuit configured to analyze even-numbered quantized outputs in the second quantized outputs, so as to generate a first portion of the adjustment signals; and 
 a second adjusting circuit configured to analyze odd-numbered quantized outputs in the second quantized outputs, so as to generate a second portion of the adjustment signals; 
 wherein the first adjusting circuit comprises:
 a delay circuit, configured to delay the last one of the even-numbered quantized outputs, so as to generate a delayed quantized output; 
 a plurality of arithmetic circuits, configured to sequentially receive two signals in the delayed quantized output and the even-numbered quantized outputs, so as to respectively generate a plurality of difference signals, wherein the difference signals are associated with the time difference information; 
 a plurality of absolute value circuits, wherein each of the plurality of absolute value circuits are configured to perform an absolute value operation according to a corresponding difference signal among the difference signals, so as to generate a corresponding one of a plurality of absolute value signals; 
 a plurality of statistics circuits, wherein each of the plurality of statistics circuits is configured to receive a corresponding absolute value signal among the absolute value signals within a predetermined period of time, and perform a statistics operation to output a corresponding one of a plurality of calculation signals; 
 an averaging circuit, configured to average the calculation signals to generate a reference signal; and 
 a plurality of comparator circuits, which respectively compare the calculation signals with the reference signal to generate a plurality of detection signals. 
 
 
 
     
     
       2. The analog-to-digital converter device of  claim 1 , wherein the first adjusting circuit outputs the detection signals as the first portion of the adjustment signals. 
     
     
       3. The analog-to-digital converter device of  claim 1 , wherein the skew adjusting circuitry further comprises:
 a plurality of filter circuits configured to generate a plurality of trigger signals according to the detection signals and at least one threshold; and 
 a plurality of integrator circuits, wherein each of the integrator circuits is configured to accumulate a corresponding trigger signal among the trigger signals, and to output the accumulated corresponding trigger signal as a corresponding adjustment signal in the first portion of the adjustment signals. 
 
     
     
       4. The analog-to-digital converter device of  claim 3 , wherein each of the filter circuits is configured to accumulate a corresponding detection signal among the detection signals, and output the accumulated corresponding detection signal as a corresponding one of the trigger signals when the accumulated corresponding detection signal is greater than the at least one threshold. 
     
     
       5. The analog-to-digital converter device of  claim 1 , wherein a circuit structure of the second adjusting circuit is the same as a circuit structure of the first adjusting circuit. 
     
     
       6. The analog-to-digital converter device of  claim 1 , wherein the analog-to-digital converter circuitries operate as a time interleaved analog-to-digital converter. 
     
     
       7. A clock skew calibration method, comprising:
 performing at least one calibration operation according to a plurality of first quantized outputs, the plurality of first quantized outputs being output from a plurality of analog-to-digital converter circuitries according to a plurality of clock signals, so as to generate a plurality of second quantized outputs; and 
 analyzing a time difference information of the clock signals within even-numbered sampling periods according to the second quantized outputs, so as to generate a plurality of adjustment signals to reduce a clock skew in the analog-to-digital converter circuitries, wherein generating the adjustment signals comprises:
 analyzing even-numbered quantized outputs in the second quantized outputs, so as to generate a first portion of the adjustment signals; and 
 analyzing odd-numbered quantized outputs in the second quantized outputs, so as to generate a second portion of the adjustment signals; 
 wherein generating the first portion of the adjustment signals comprises:
 delaying the last one of the second quantized outputs, so as to generate a delayed quantized output; 
 sequentially generating a plurality of difference signals according to two signals in the delayed quantized output and the even-numbered quantized outputs, wherein the difference signals are associated with the time difference information; 
 performing an absolute value operation according to a corresponding difference signal among the difference signals, so as to generate a corresponding one of a plurality of absolute value signals; 
 receiving a corresponding absolute value signal among the absolute value signals, and perform a statistics operation to output a corresponding one of a plurality of calculation signals; 
 averaging the calculation signals to generate a reference signal; and 
 comparing the calculation signals with the reference signal to generate a plurality of detection signals. 
 
 
 
     
     
       8. The clock skew calibration method of  claim 7 , wherein the detection signals are output as the adjustment signals. 
     
     
       9. The clock skew calibration method of  claim 7 , further comprising:
 generating a plurality of trigger signals according to the detection signals and at least one threshold; and 
 accumulating a corresponding trigger signal among the trigger signals to output as a corresponding adjustment signal in the first portion of the adjustment signals. 
 
     
     
       10. The clock skew calibration method of  claim 9 , wherein generating the trigger signals comprises:
 accumulating a corresponding detection signal among the detection signals, and output the accumulated corresponding detection signal as a corresponding one of the trigger signals when the accumulated corresponding detection signal is greater than the at least one threshold. 
 
     
     
       11. The clock skew calibration method of  claim 7 , wherein the analog-to-digital converter circuitries operate as a time interleaved analog-to-digital converter.