Memory device including load generator and method of operating the same

Abstract

A memory device includes a load generator and a memory controller. The load generator outputs loads for first accesses directed to a memory, irrespective of attributes and characteristics of master devices. The load generator outputs the loads at a constant bandwidth without a change in a bandwidth for outputting the loads. The memory controller receives the loads from the load generator, or receives requests for second accesses directed to the memory from the master devices through a bus. The memory controllers processes the loads such that operations associated with the first accesses are performed in the memory, or processes the requests such that operations associated with the second accesses are performed in the memory. The memory controller processes the loads in a manner which is identical to a manner of processing the requests.

What is claimed is: 
     
       1. A memory device comprising:
 a load generator configured to generate a plurality of memory test loads for a plurality of first memory accesses directed to at least one memory device, the plurality of memory test loads mimicking a plurality of memory access requests for a plurality of second memory accesses from a plurality of master devices of at least two different device types directed to the at least one memory device, each of the plurality of memory test loads being generated based on a respective device type of the corresponding master device of the plurality of master devices; and 
 a memory controller configured to,
 receive the memory test loads from the load generator, and 
 process the memory test loads, the processing the memory test loads including performing memory operations associated with the plurality of first memory accesses on the at least one memory device, 
 wherein the memory controller is further configured to process the memory test loads in a manner which is identical to a manner of processing the memory access requests. 
 
 
     
     
       2. The memory device of  claim 1 , wherein
 each of the memory test loads of the plurality of the memory test loads includes a data pattern for testing the at least one memory device based on the plurality of first memory accesses using a desired bandwidth with regard to the at least one memory device; and 
 a data format of the memory test loads is based on a data format of the memory access requests output from the plurality of master devices. 
 
     
     
       3. The memory device of  claim 1 , further comprising:
 a switch circuit configured to selectively transfer the memory test loads from the load generator or the memory access requests from the plurality of master devices from a bus to the memory controller. 
 
     
     
       4. The memory device of  claim 3 , further comprising:
 a register configured to output an enable signal to the load generator and the switch circuit, wherein 
 the load generator is further configured to output the memory test loads based on the enable signal, and 
 the switch circuit is further configured to transfer the memory test loads to the memory controller based on the enable signal. 
 
     
     
       5. The memory device of  claim 4 , wherein
 the register is further configured to output a pattern control signal to the load generator, the pattern control signal including a desired data pattern; and 
 the load generator is further configured to output the memory test loads based on the desired data pattern. 
 
     
     
       6. The memory device of  claim 1 , wherein the load generator is further configured to output the memory test loads in response to a first clock among a plurality of clocks for operating the plurality of master devices and a bus. 
     
     
       7. The memory device of  claim 6 , wherein a frequency of the first clock is the highest among frequencies of the plurality of clocks. 
     
     
       8. The memory device of  claim 1 , wherein the load generator is further configured to output the memory test loads in response to a bus clock for operating a bus. 
     
     
       9. The memory device of  claim 8 , wherein a frequency of the bus clock is lower than a frequency of a memory controller clock for operating the memory controller. 
     
     
       10. The memory device of  claim 9 , wherein
 the memory controller comprises a buffer memory configured to sequentially store and output data values which correspond to the memory test loads; 
 the buffer memory is further configured to store the data values until a data size of the data values reach a reference data size; and 
 in response to the data size of the data values stored in the buffer memory reaching the reference data size,
 the buffer memory is further configured to output the stored data values of the reference data size in response to a release signal received from the load generator, and 
 the memory controller is further configured to process the memory test loads corresponding to the output data values in response to the memory controller clock. 
 
 
     
     
       11. A memory controller configured to control a memory device, the memory controller comprising:
 a load generator configured to generate a plurality of memory test loads for a plurality of first memory accesses directed to the memory device, the plurality of memory test loads mimicking a plurality of memory access requests for a plurality of second memory accesses from a plurality of second master devices of at least two different device types directed to the memory device, each of the plurality of memory test loads being generated based on a respective device type of the corresponding master device of the plurality of master devices; 
 an interface circuit configured to receive the memory test loads from the load generator; and 
 processing circuits configured to,
 receive the memory test loads from the interface circuit, and 
 process the memory test loads such that memory operations associated with the plurality of first memory accesses are performed in the memory device, 
 
 wherein, in response to a test enable signal,
 the load generator is further configured to output the memory test loads, the memory test loads having a data format equivalent to a data format of the memory access requests from the plurality of master devices, and 
 the interface circuit is further configured to receive the memory test loads from the load generator, without receiving the memory access requests from the plurality of master devices. 
 
 
     
     
       12. The memory controller of  claim 11 , wherein the load generator is further configured to output the memory test loads at a constant bandwidth rate for outputting the memory test loads. 
     
     
       13. The memory controller of  claim 11 , wherein the processing circuits are further configured to process each of the memory test loads only once. 
     
     
       14. The memory controller of  claim 11 , wherein the receiving and the processing the memory test loads at the processing circuits are exclusive to receiving and processing the memory access requests at the processing circuits. 
     
     
       15. A method of operating a memory device, the method comprising:
 receiving an enable signal for a test of the memory device; 
 generating, by a load generator, a plurality of memory test loads simulating a plurality of memory accesses directed to the memory device from a plurality of master devices of at least two different device types based on the enable signal, the generating the plurality of the memory test loads including outputting the plurality of memory test loads at a constant bandwidth rate, and each of the plurality of the memory test loads is generated on a respective device type of the corresponding master device of the plurality of master devices; and 
 processing, by a memory controller of the memory device, the memory test loads, the processing the memory test loads including performing memory operations associated with memory accesses corresponding to the memory test loads. 
 
     
     
       16. The method of  claim 15 , wherein the constant bandwidth rate is a maximum bandwidth rate of the memory device. 
     
     
       17. The method of  claim 15 , further comprising:
 receiving a pattern control signal associated with a data pattern; and 
 wherein the generating the memory test loads further comprises generating the memory test loads based on the data pattern indicated by the pattern control signal. 
 
     
     
       18. The method of  claim 15 , further comprising:
 blocking memory access to the memory device from a plurality of master devices through a bus based on the enable signal. 
 
     
     
       19. The method of  claim 15 , wherein
 the outputting the memory test loads comprises outputting the memory test loads in response to a first clock, where a frequency of the first clock is lower than a frequency of a second clock for operating the memory controller; and 
 the processing the memory test loads comprises,
 buffering data values corresponding to the output memory test loads in a buffer memory, until a data size of the buffered data values reach a reference data size, and 
 processing, in response to the second clock, the buffered data values where the data size has reached the reference data size. 
 
 
     
     
       20. The method of  claim 19 , wherein
 the buffering the data values comprises,
 increasing, by the load generator, a count value whenever the data values are buffered in the buffer memory, and 
 outputting, by the load generator, a release signal when the count value reaches a reference value; 
 
 the processing the buffered data values comprises processing the buffered data values in response to the release signal; and 
 the reference value is associated with the reference data size.