Driving circuit and display device including the same

Abstract

Provided is a scan driving circuit including a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits including: a first transistor configured to receive a prior scan signal in synchronization with a first clock signal and to respond to an enable level of the prior scan signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; a second transistor coupled between the first transistor and a first voltage; and a third transistor coupled to a gate of the second transistor and configured to be turned on by a first signal. A width of a first wire configured to transfer the first clock signal and a width of a second wire configured to transfer the second clock signal are larger than that of a third wire configured to transfer the first signal.

What is claimed is: 
     
       1. A scan driver comprising:
 a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits comprising:
 a first transistor configured to receive an input signal in synchronization with a first clock signal and to respond to an enable level of the input signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; 
 a second transistor electrically connected between the first transistor and a first voltage; 
 a third transistor electrically connected between a gate of the second transistor and a second voltage; and 
 a fourth transistor electrically connected between a gate of the first transistor and the first voltage; 
 
 a first capacitor and a second capacitor; 
 a first wire configured to transfer the first clock signal; 
 a second wire configured to transfer the second clock signal; 
 a third wire configured to transfer the first voltage; and 
 a fourth wire configured to transfer the second voltage, 
 wherein a width of the third wire is larger than a width of the fourth wire, wherein the first voltage and the second voltage are DC voltages and the first voltage is higher than the second voltage, 
 wherein the first, second, third, and fourth transistor are p-channel transistors. 
 
     
     
       2. The scan driver of  claim 1 , wherein the first capacitor is connected between the gate of the first transistor and a source of the first transistor. 
     
     
       3. The scan driver of  claim 1 , wherein the second capacitor is connected between the gate of the second transistor and a source of the second transistor. 
     
     
       4. The scan driver of  claim 1 , wherein a gate of the third transistor is coupled to the third wire. 
     
     
       5. A scan driver comprising:
 a first wire configured to transfer a first clock signal; 
 a second wire configured to transfer a first initialization signal; 
 a first transistor comprising an electrode coupled to the first wire; 
 a second transistor comprising a gate electrode coupled to the second wire; 
 a third transistor coupled between a gate electrode of the first transistor and a first voltage; 
 a fourth wire configured to transfer a first voltage; 
 a fifth wire configured to transfer a second voltage; and 
 a sixth transistor comprising a gate electrode coupled to the second transistor, an electrode coupled to another electrode of the first transistor, and another electrode coupled to the fourth wire, wherein a width of the fourth wire is larger than a width of the fifth wire, 
 wherein the first voltage and the second voltage are DC voltages and the first voltage is higher than the second voltage, 
 wherein a width of the first wire configured to transfer the first clock signal is larger than a width of the second wire configured to transfer the first initialization signal, and 
 wherein the first wire and the second wire extend in parallel to each other along a side of an area where the first, second, third, fourth, fifth and sixth transistor are disposed, 
 wherein the first, second, third, fourth, fifth and sixth transistor are p-channel transistors. 
 
     
     
       6. The scan driver of  claim 5 , further comprising:
 a third wire configured to transfer a second clock signal; and 
 a fourth transistor comprising an electrode coupled to the third wire, 
 wherein a width of the third wire is larger than the width of the second wire. 
 
     
     
       7. The scan driver of  claim 6 , further comprising:
 a fifth transistor comprising a gate electrode coupled to the third wire, 
 wherein a gate electrode of the first transistor is coupled to an electrode of the fifth transistor. 
 
     
     
       8. The scan driver of  claim 5 , wherein an electrode of the second transistor is coupled to the fifth wire, and another electrode of the second transistor is coupled to the gate electrode of the sixth transistor. 
     
     
       9. A scan driver comprising:
 a first wire configured to transfer a first voltage; 
 a second wire configured to transfer a second voltage lower than the first voltage; 
 a first transistor comprising an electrode coupled to the first wire; and 
 a second transistor comprising an electrode coupled to a gate electrode of the first transistor, another electrode coupled to the second wire; and 
 a third transistor coupled between the gate electrode of the first transistor and a first voltage, 
 wherein a width of the first wire configured to transfer the first voltage is larger than a width of the second wire configured to transfer the second voltage, 
 wherein the first wire and the second wire extend in parallel to each other along an entire side of the first transistor, an entire side of the second transistor, and an entire side of the third transistor, 
 wherein an electrode of the third transistor is coupled to a gate electrode of the second transistor, another electrode of the third transistor is configured to receive a second voltage, a gate of the third transistor is coupled to a third wire, a width of a fourth wire configured to transfer the first voltage is larger than a width of a fifth wire configured to transfer the second voltage, wherein the first voltage and the second voltage are DC voltages, and the first voltage is higher than the second voltage. 
 
     
     
       10. A scan driver comprising:
 a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits comprising: 
 a first transistor configured to receive an input signal in synchronization with a first clock signal and to respond to an enable level of the input signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; 
 a second transistor electrically connected between the first transistor and a first voltage in series; 
 a third transistor electrically connected to a gate of the second transistor; 
 a fourth transistor electrically connected between the gate of the first transistor and the first voltage; 
 a fifth transistor electrically connected to the first voltage; 
 a sixth transistor electrically connected to the gate of the first transistor and configured to be turned on by the first clock signal, 
 a first wire configured to transfer the first clock signal; 
 a second wire configured to transfer the second clock signal; 
 a third wire configured to transfer the first voltage; 
 a fourth wire configured to transfer a second voltage, wherein the first voltage is higher than the second voltage, 
 wherein the first, second, third, fourth, fifth and sixth transistor are p-channel transistors, 
 wherein a width of a third wire is larger than a width of a fourth wire, and 
 wherein the first voltage and the second voltage are DC voltages. 
 
     
     
       11. The scan driver of  claim 10 , further consisting of
 a first capacitor configured to be connected between the gate of the first transistor and a source electrode of the first transistor; and 
 a second capacitor configured to be connected between the gate of the second transistor and the source electrode of the second transistor. 
 
     
     
       12. A scan driver comprising:
 a plurality of unit scan driving circuits, wherein one unit scan driving circuit comprising: 
 a first transistor configured to receive an input signal in synchronization with a first clock signal and to respond to an enable level of the input signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; 
 a second transistor electrically connected between the first transistor and a first voltage in series; 
 a third transistor electrically connected between a gate of the second transistor and a second voltage; and 
 a fourth transistor electrically connected to the gate of the first transistor and configured to be turned on by the first clock signal to transfer a first signal; 
 a first capacitor electrically connected between the gate of the first transistor and a source of the first transistor; and 
 a second capacitor electrically connected between the gate of the second transistor and the source of the second transistor; 
 a first wire configured to transfer the first clock signal; 
 a second wire configured to transfer the second clock signal; 
 a third wire configured to transfer the first voltage; and 
 a fourth wire configured to transfer the second voltage, 
 wherein the first, second, and third transistor are p-channel transistors, 
 wherein a width of a third wire is larger than a width of a fourth wire, and 
 wherein the first voltage and the second voltage are DC voltages. 
 
     
     
       13. The scan driver of  claim 12 , wherein the unit scan driving circuit further comprising:
 a fifth transistor electrically connected between a gate of the first transistor and the first voltage.