High-speed and low-noise dynamic comparator

Abstract

The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage. In the present disclosure, a substrate bootstrap technology of MOS transistors is used, thereby reducing on resistances of the MOS transistors and improving the comparator speed; threshold voltages of the input transistors of the comparator are reduced, transconductance of the input transistors is increased, thereby reducing equivalent input noise of the comparator, and as a common-mode voltage of the comparator changes, a comparison delay changes relatively little.

What is claimed is: 
     
       1. A high-speed and low-noise dynamic comparator, comprising:
 an input unit, comprising an input NMOS transistor and an input PMOS transistor; 
 a latch unit, comprising a latching NMOS transistor and a latching PMOS transistor, wherein the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; 
 a pull-up unit coupled with the input unit and the latch unit, comprising a pull-up PMOS transistor connected to the input NMOS transistor; 
 a pull-down unit coupled with the input unit, comprising a pull-down NMOS transistor connected to the input PMOS transistor; 
 a first signal control end, for generating a first control signal; 
 a second signal control end connected with the pull-up unit, for generating a second control signal; and 
 a substrate bootstrap voltage generation circuit connected with the first signal control end, for generating a substrate bootstrap voltage and comprising a first bootstrap voltage generation circuit connected to an NMOS transistor substrate and a second bootstrap voltage generation circuit connected to a PMOS transistor substrate; 
 wherein the first bootstrap voltage generation circuit comprises a bootstrap voltage NMOS transistor and a first capacitor, wherein
 a gate of the bootstrap voltage NMOS transistor is connected to a reverse signal end of the first control signal, 
 a drain of the bootstrap voltage NMOS transistor is connected to the first signal control end through the first capacitor, and 
 a source of the bootstrap voltage NMOS transistor is grounded; 
 
 the second bootstrap voltage generation circuit comprises a bootstrap voltage PMOS transistor and a second capacitor, wherein
 a gate of the bootstrap voltage PMOS transistor is connected to the first signal control end, 
 a source of the bootstrap voltage PMOS transistor is connected to a power source, and 
 a drain of the bootstrap voltage PMOS transistor is connected to the reverse signal end of the first control signal through the second capacitor; 
 
 the pull-up PMOS transistor comprises a first pull-up PMOS transistor, a second pull-up PMOS transistor, and a third pull-up PMOS transistor, wherein
 a gate of the first pull-up PMOS transistor is connected to the second signal control end, 
 a source of the first pull-up PMOS transistor is connected to a power source VDD, 
 a drain of the first pull-up PMOS transistor is connected to the latch unit; 
 a gate of the second pull-up PMOS transistor is connected to the second signal control end, 
 a source of the second pull-up PMOS transistor is connected to the power source VDD, 
 a drain of the second pull-up PMOS transistor is connected to the latch unit, 
 a gate of the third pull-up PMOS transistor is connected to a reverse signal end of the second signal control end, 
 a source of the third pull-up PMOS transistor is connected to the power source VDD, and 
 a drain of the third pull-up PMOS transistor is connected to the latch unit; 
 
 when the comparator is in a reset state,
 the first control signal and the second control signal are low level signals, 
 substrate voltages of all NMOS transistors are 0, 
 substrate voltages of all PMOS transistors are 1, 
 a voltage at two ends of the first capacitor is 0, and 
 a voltage at two ends of the second capacitor is 1; and 
 
 when the comparator is in a comparison state,
 a substrate voltage of the input NMOS transistor and a substrate voltage of the pull-down NMOS transistor are coupled to a high potential, and 
 
 a substrate voltage of the input PMOS transistor and a substrate voltage of the third pull-up PMOS transistor are coupled to a low potential. 
 
     
     
       2. The high-speed and low-noise dynamic comparator as in  claim 1 , wherein
 the pull-down NMOS transistor comprises a first pull-down NMOS transistor; 
 the latching NMOS transistor comprises a first latching NMOS transistor and a second latching NMOS transistor; 
 the latching PMOS transistor comprises a first latching PMOS transistor and a second latching PMOS transistor; 
 a gate of the first latching NMOS transistor is separately connected to a gate of the first latching PMOS transistor, a drain of the second latching PMOS transistor, and a drain of the second latching NMOS transistor; 
 a gate of the second latching NMOS transistor is separately connected to a gate of the second latching PMOS transistor, a drain of the first latching PMOS transistor, and a drain of the first latching NMOS transistor; 
 a source of the first latching NMOS transistor, a source of the second latching NMOS transistor, and a drain of the first pull-down NMOS transistor are connected to each other; 
 the drain of the first pull-down NMOS transistor is separately connected to the source of the first latching NMOS transistor and the source of the second latching NMOS transistor, 
 the drain of the first pull-down NMOS transistor is grounded; and 
 a source of the first latching PMOS transistor, a source of the second latching PMOS transistor, and a drain of the third pull-up PMOS transistor are connected to each other. 
 
     
     
       3. The high-speed and low-noise dynamic comparator as in  claim 2 , further comprising a delay unit, wherein
 the input NMOS transistor comprises a first input NMOS transistor and a second input NMOS transistor; 
 the input PMOS transistor comprises a first input PMOS transistor and a second input PMOS transistor; 
 the pull-down NMOS transistor further comprises a second pull-down NMOS transistor; 
 a source of the first input NMOS transistor, a source of the second input NMOS transistor, and a drain of the second pull-down NMOS transistor are connected to each other; 
 a source of the second pull-down NMOS transistor is grounded; 
 a voltage signal DP and a voltage signal DN are respectively connected to two input ends of an XNOR gate; 
 an output end of the XNOR gate and a first control signal are respectively connected to two input ends of an AND gate; and 
 an output end of the AND gate is separately connected to a gate of the second pull-down NMOS transistor and an input end of the delay unit. 
 
     
     
       4. The high-speed and low-noise dynamic comparator as in  claim 3 , wherein
 the input PMOS transistor comprises the first input PMOS transistor and the second input PMOS transistor, wherein
 a gate of the first input PMOS transistor is connected to a voltage input end VIP; 
 a source of the first input PMOS transistor is connected to the source of the first latching PMOS transistor; 
 a drain of the first input PMOS transistor is separately connected to the drain of the first latching PMOS transistor, the drain of the first pull-up PMOS transistor, the drain of the first latching NMOS transistor, the gate of the second latching NMOS transistor, the gate of the second latching PMOS transistor, and a drain of the first input NMOS transistor; 
 the drain of the first input PMOS transistor is further connected to a reverse signal end of the voltage signal DP; 
 a gate of the second input PMOS transistor is connected to a voltage input end VIN; 
 a source of the second input PMOS transistor is connected to the source of the second latching PMOS transistor; 
 a drain of the second input PMOS transistor is separately connected to the drain of the second latching PMOS transistor, the drain of the second pull-up PMOS transistor, the gate of the first latching NMOS transistor, the gate of the first latching PMOS transistor, and a drain of the second input NMOS transistor; and 
 the drain of the second input PMOS transistor is further connected to a reverse signal end of the voltage signal DN. 
 
 
     
     
       5. The high-speed and low-noise dynamic comparator as in  claim 4 , wherein
 the first bootstrap voltage generation circuit is separately connected to a substrate of the first input NMOS transistor, a substrate of the second input NMOS transistor, and a substrate of the second pull-down NMOS transistor; and 
 the second bootstrap voltage generation circuit is separately connected to a substrate of the third pull-up PMOS transistor, a substrate of the first input PMOS transistor, a substrate of the second input PMOS transistor, and a substrate of the first pull-down NMOS transistor. 
 
     
     
       6. The high-speed and low-noise dynamic comparator as in  claim 5 , wherein when the comparator is in a comparison state,
 the first control signal and the second control signal are 1; 
 the first pull-down NMOS transistor, the second pull-down NMOS transistor, and the third pull-up PMOS transistor are turned on; 
 the first pull-up PMOS transistor and the second pull-up PMOS transistor are turned off; 
 the bootstrap voltage NMOS transistor and the bootstrap voltage PMOS transistor are turned off; 
 a first bootstrap voltage generated by the first bootstrap voltage generation circuit is coupled by the first capacitor to a high potential; 
 a second bootstrap voltage generated by the second bootstrap voltage generation circuit is coupled by the second capacitor to a low potential; 
 the substrate voltages of the first input NMOS transistor, the second input NMOS transistor, the first pull-down NMOS transistor, and the second pull-down NMOS transistor are coupled to a high potential; and 
 the substrate voltages of the first input PMOS transistor, the second input PMOS transistor, and the third pull-up PMOS transistor are coupled to a low potential.