Radar level indicator having a short measurement time

Abstract

A radar level indicator comprising a processor, an analogue-digital converter circuit and an intermediate memory connected therebetween. The intermediate memory is configured to receive digital signals from the analogue-digital converter circuit at a first data rate. The processor is configured to read out the intermediate memory at a second data rate that is different from the first data rate. It is thus possible to reduce the transmission time while maintaining the same energy requirement.

The invention claimed is: 
     
       1. A method for fill level measurement, limit measurement, pressure measurement or flow measurement, in which measurement data are acquired and processed, said method comprising:
 acquiring fill level, limit level, pressure or flow measurement data; 
 activating an intermediate memory by supplying the intermediate memory with an external operating clock signal and/or supply voltage; 
 receiving, in the intermediate memory, digital signals from an analogue-digital converter circuit at a first data rate, the digital signals corresponding to the acquired fill level, limit level, pressure or flow measurement data; 
 activating a processor after receiving the digital signals in the intermediate memory; 
 reading out, by the processor, data from the intermediate memory at a second data rate that is smaller than the first data rate; 
 deactivating the intermediate memory by separating the intermediate memory from the external operating clock signal and/or the external supply voltage; 
 calculating, by the processor and after deactivating the intermediate memory, a measured value from the digital signals and outputting the measured value; 
 putting the processor into a sleep mode; and 
 activating the intermediate memory. 
 
     
     
       2. A non-transitory computer-readable medium, having stored thereon a program element that when executed by a computer causes the computer to implement the method according to  claim 1 . 
     
     
       3. The fill level measurement according to  claim 1 , wherein the measured value calculated by the processor is a limit measurement. 
     
     
       4. The fill level measurement according to  claim 1 , wherein the measured value calculated by the processor is a pressure measurement. 
     
     
       5. The fill level measurement according to  claim 1 , wherein the measured value calculated by the processor is a flow measurement. 
     
     
       6. A radar level indicator, comprising:
 at least one processor; 
 at least one analogue-digital converter circuit; and 
 at least one intermediate memory that is arranged between the processor and the analogue-digital converter circuit, 
 wherein the intermediate memory is activated by a supplied external operating clock signal and/or supply voltage and deactivated by separating the intermediate memory from the external operating clock signal and/or the external supply voltage, 
 wherein the intermediate memory is configured to receive digital signals from the analogue-digital converter circuit at a first data rate, the digital signals corresponding to acquired fill level, limit level, pressure or flow measurement data, 
 wherein the processor is configured to read out the intermediate memory at a second data rate that is smaller than the first data rate, 
 wherein the processor is configured to, after the intermediate memory is deactivated, calculate a measured value from the digital signals and output the measured value, and 
 wherein the processor is put into a sleep mode and the intermediate memory is activated in response to the output of the measured value. 
 
     
     
       7. The radar level indicator according to  claim 6 ,
 wherein the first data rate is higher than the second data rate. 
 
     
     
       8. The radar level indicator according to  claim 6 ,
 wherein the analogue-digital converter circuit comprises a differential interface and is configured to generate the digital signals in the form of a differential output signal. 
 
     
     
       9. The radar level indicator according to  claim 6 ,
 wherein the intermediate memory comprises a programmable logic component. 
 
     
     
       10. The radar level indicator according to  claim 6 ,
 wherein the digital signals are digital sampling values of a received signal of the radar level indicator. 
 
     
     
       11. The radar level indicator according to  claim 6 ,
 wherein the intermediate memory is configured to process the received digital signals. 
 
     
     
       12. The radar level indicator according to  claim 6 ,
 wherein the intermediate memory comprises a first in, first out memory and/or a circular buffer. 
 
     
     
       13. The radar level indicator according to  claim 6 , wherein the processor is configured to connect to a 4-20 mA two-conductor interface supplying power and outputting the measured values. 
     
     
       14. A method for fill level measurement, limit measurement, pressure measurement or flow measurement, in which measurement data are acquired and processed, said method comprising:
 acquiring fill level, limit level, pressure or flow measurement data; 
 in response to the acquiring, activating an intermediate memory by supplying the intermediate memory with an external operating clock signal and/or supply voltage; 
 receiving, in the intermediate memory, digital signals from an analogue-digital converter circuit at a first data rate, the digital signals corresponding to the acquired fill level, limit level, pressure or flow measurement data; 
 in response to the receiving the digital signals in the intermediate memory, activating a processor; 
 reading out, by the processor, data of the digital signals from the intermediate memory at a second data rate that is lower than the first data rate; 
 in response to the reading out, deactivating the intermediate memory by separating the intermediate memory from the external operating clock signal and/or the external supply voltage; 
 calculating, by the processor and after deactivating the intermediate memory, a measured value from the digital signals and outputting the measured value; and 
 in response to the outputting, putting the processor into a sleep mode and activating the intermediate memory. 
 
     
     
       15. The method according to  claim 14 , wherein the data of the digital signals read out by the reading out step is unmodified.