Printed wiring board and method for manufacturing same

Abstract

A printed wiring board in the present disclosure includes a core layer, a first buildup layer, a second buildup layer, and a through hole. The core layer has a conductor circuit located on a surface of an insulator. The first buildup layer containing a first resin is laminated on a surface of the core layer. The second buildup layer containing a second resin is laminated on a surface of the first buildup layer. The through hole extends through the core layer, the first buildup layer, and the second buildup layer. The first resin and the second resin are different from each other. The second buildup layer includes a plurality of filled vias filled with a conductor which are located around a circumference of an opening of the through hole.

The invention claimed is: 
     
       1. A printed wiring board, comprising: a core layer comprising a conductor circuit located on a surface of an insulator; a first buildup layer containing a first resin which is laminated on a surface of the core layer; a second buildup layer containing a second resin which is laminated on a surface of the first buildup layer; a first conductor layer laminated on the surface of the first buildup layer between the first and second buildup layers; and a through hole extending through the core layer, the first buildup layer, and the second buildup layer, and a second conductor layer extending continuously on an exposed bottom surface of the second buildup layer, on an inner surface of the through hole and on a top surface of the printed wiring board opposite the exposed bottom surface of the second buildup layer, wherein the first resin and the second resin are different from each other, the second buildup layer comprises a plurality of vias which are filled with a conductor and located on an identical circumference equally spaced around an opening of the through hole, and wherein the plurality of vias, which are filled with the conductor, are electrically independent, are directly connected to the first conductor layer, and the filled vias are not electrically connected to the second conductor layer. 
     
     
       2. The printed wiring board according to  claim 1 , wherein at least two pieces of the filled vias are arranged around the circumference of the opening of the through hole. 
     
     
       3. The printed wiring board according to  claim 1 , wherein a plurality of the filled vias are arranged on an identical circumference around the through hole. 
     
     
       4. The printed wiring board according to  claim 1 , wherein a wall surface of the through hole and a wall surface of each of the filled vias are separated by a distance of at least 0.3 mm. 
     
     
       5. The printed wiring board according to  claim 1 , wherein a distance between wall surfaces of the filled vias adjacent to each other is at least 0.3 mm. 
     
     
       6. The printed wiring board according to  claim 1 , wherein a resin constituting the insulator of the core layer and the first resin constituting the first buildup layer are identical. 
     
     
       7. The printed wiring board according to  claim 1 , wherein
 the first buildup layer is located on both upper and lower surfaces of the core layer, and 
 the second buildup layer located on a surface of the first buildup layer located on one or both of the upper and lower surfaces. 
 
     
     
       8. The printed wiring board according to  claim 1 , wherein the second buildup layer is located on a surface of the first buildup layer located on one surface of the core layer. 
     
     
       9. The printed wiring board according to  claim 1 , wherein the first buildup layer comprises at least one layer containing the first resin. 
     
     
       10. The printed wiring board according to  claim 1 , wherein the second resin has a greater thermal expansion coefficient than the first resin. 
     
     
       11. The printed wiring board according to  claim 1 , wherein the conductor of each of the plurality of filled vias is electrically independent from the conductor circuit. 
     
     
       12. The printed wiring board according to  claim 1 , wherein the plurality of filled vias push the second buildup layer against a side of the core layer. 
     
     
       13. The printed wiring board according to  claim 1 , wherein the plurality of vias are electrically independent from the through hole and only extend through the second buildup layer. 
     
     
       14. A method of manufacturing a printed wiring board, comprising: obtaining a core layer by forming a conductor circuit on a surface of an insulator; laminating a first buildup layer containing a first resin on at least one surface of the core layer; laminating a first conductor layer on the at least one surface of the first buildup layer, laminating a second buildup layer containing a second resin, different from the first resin, on a surface of the first buildup layer and the first conductor layer; forming a through hole extending through the core layer and the first and second buildup layers; forming a second conductor layer extending continuously on an exposed bottom surface of the second buildup layer, on an inner surface of the through hole and on a top surface of the printed wiring board opposite the exposed bottom surface of the second buildup layer; and forming a plurality of vias which are filled with a conductor and located on an identical circumference equally spaced around an opening of the through hole in the second buildup layer, wherein the plurality of vias, which are filled with the conductor, are electrically independent, are directly connected to the first conductor layer, and are not electrically connected to the second conductor layer. 
     
     
       15. The method of manufacturing a printed wiring board according to  claim 14 , wherein the second buildup layer is a resin-attached copper foil. 
     
     
       16. The method of manufacturing a printed wiring board according to  claim 14 , wherein the second buildup layer is a double-layer substrate. 
     
     
       17. The method according to  claim 14 , wherein the plurality of vias are electrically independent from the through hole and only extend through the second buildup layer.