Manufacturing method for a TFT array substrate and TFT array substrate

Abstract

A manufacturing method for TFT array substrate and TFT array substrate are disclosed. After depositing an electrode material layer and a metal material layer on the gate insulation layer and the active layer in sequence after the active layer above the gate electrode is formed. A photoresist pattern is formed on the metal material layer. The photoresist pattern includes a first and second photoresist blocks with different thicknesses. The metal material layer and the electrode material layer are etched using the photoresist pattern to form a contact electrode and pixel electrodes connected with two ends of the active layer and the source/drain electrodes on the contact electrode. The process is simple and can effectively reduce the contact resistance between the source/drain and the active layer and improve the quality of the product.

What is claimed is: 
     
       1. A manufacturing method for a TFT array substrate, comprising steps of:
 step (S 1 ), providing a substrate, forming a gate electrode and a gate insulation layer covering the gate electrode on the substrate; 
 step (S 2 ), forming an active layer on the gate insulation layer, wherein the active layer comprises an amorphous silicon material layer and a doped amorphous silicon layer; 
 step (S 3 ), sequentially depositing an electrode material layer and a metal material layer on the gate insulation layer and the active layer such that the electrode material layer is in contact with the doped amorphous silicon layer; forming a photoresist pattern on the metal material layer, wherein the photoresist pattern includes a first photoresist block and a second photoresist block which are separate from each other; a projection of a portion of the first photoresist block in a vertical direction is overlapped with one end of the active layer, and a projection of a portion of the second photoresist block in the vertical direction is overlapped with an opposite end of the active layer; a thickness of the first photoresist block is greater than a thickness of the second photoresist block; and 
 step (S 4 ), etching the metal material layer and the electrode material layer using the photoresist pattern as a mask to remove a portion of the metal material layer and a portion of the electrode material layer that are not covered by the photoresist pattern; ashing the photoresist pattern to remove the second photoresist block so as to form an ashed photoresist pattern; etching the metal material layer using the ashed photoresist pattern as a mask to remove a portion of the metal material layer that is not covered by the ashed photoresist pattern in order to form a contact electrode and a pixel electrode respectively connected with the one end and the opposite end of the active layer and a source/drain electrode located on the contact electrode; 
 wherein the portion of the metal material layer that is not covered by the photoresist pattern is removed with a first removing operation and the portion of the electrode material layer that is not covered by the photoresist pattern is removed with a second removing operation that is different from the first removing operation, and wherein a portion of the doped amorphous silicon layer is not covered by the photoresist pattern and corresponds to the portion of the electrode material layer that is not covered by the photoresist pattern, and the portion of the doped amorphous silicon material layer is removed simultaneously with the portion of the electrode material layer with the second removing operation, and the removal of the portion of the doped amorphous silicon layer is separate from the removal of the portion of the metal material layer that is not covered by the photoresist pattern. 
 
     
     
       2. The manufacturing method for a TFT array substrate according to  claim 1 , wherein the step (S 4 ) further includes a step of removing the ashed photoresist pattern. 
     
     
       3. The manufacturing method for a TFT array substrate according to  claim 2 , wherein the method further comprises a step (S 5 ), depositing a passivation layer on the gate insulation layer, the active layer, the pixel electrode, and the source/drain electrode; forming a common electrode on the passivation layer. 
     
     
       4. The manufacturing method for a TFT array substrate according to  claim 1 , wherein a specific process of forming the gate electrode on the substrate is: depositing a gate metal layer on the substrate, and performing an exposure and development process on the gate metal layer in order to form the gate electrode;
 wherein the step (S 2 ) comprises: 
 step (S 21 ), depositing an amorphous silicon material on the gate insulation layer, and performing an exposure and development process to the amorphous silicon material to form an amorphous silicon island; 
 step (S 22 ), performing an ion doping to the amorphous silicon island to form the active layer, wherein the active layer includes the amorphous silicon material layer and the doped amorphous silicon layer located on the amorphous silicon material layer; 
 step (S 3 ), a specific process of forming the photoresist pattern on the metal material layer is: forming a photoresist material layer on the metal material layer, and patterning the photoresist material layer using a halftone mask in order to obtain the photoresist pattern. 
 
     
     
       5. The manufacturing method for a TFT array substrate according to  claim 4 , wherein in the step (S 4 ), when etching the metal material layer and the electrode material layer using the photoresist pattern as a mask in order to remove the metal material layer and the electrode material layer which are not blocked by the photoresist pattern, and also to remove the portion of the doped amorphous silicon layer that is not covered by the photoresist pattern in order to form a first contact layer and a second contact layer respectively located on two ends of the amorphous silicon material layer, wherein the contact electrode is connected to the first contact layer, and the pixel electrode is connected to the second contact layer. 
     
     
       6. The manufacturing method for a TFT array substrate according to  claim 5 , wherein in the step (S 4 ), dry etching the metal material layer using the photoresist pattern as a mask to remove the portion of the metal material layer not covered by the photoresist pattern, and then wet etching the electrode material layer and the doped amorphous silicon layer using the photoresist pattern as a mask to remove the portion of the electrode material layer and the portion of the doped amorphous silicon layer that are not covered by the photoresist pattern; dry etching the metal material layer using the ashed photoresist pattern as a mask to remove the portion of the metal material layer not covered by the ashed photoresist pattern. 
     
     
       7. The manufacturing method for a TFT array substrate according to  claim 1 , wherein a material of the gate electrode is molybdenum (Mo), a material of the gate insulation layer is silicon nitride and a material of the electrode material layer is indium tin oxide (ITO). 
     
     
       8. The manufacturing method for a TFT array substrate according to  claim 4 , wherein in the step (S 22 ), the ion doping performed to the amorphous silicon island comprises N-type ion doping. 
     
     
       9. The manufacturing method for a TFT array substrate according to  claim 4 , wherein in the step (S 22 ), the ion doping performed to the amorphous silicon island comprises N-type ion doping with phosphorus ions.