Cryogenic transmitter

Abstract

A semiconductor device includes a transmission circuit coupled between a first voltage supply node and a second voltage supply node, and suitable for outputting an output data signal corresponding to a data value to an output terminal during a data output enable period, and a switching circuit coupled between the first and second voltage supply nodes, and suitable for providing a current path between the first and second voltage supply nodes during a data output disable period.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a transmission circuit coupled between a first voltage supply node and a second voltage supply node, and suitable for outputting an output data signal corresponding to a data value to an output terminal during a data output enable period; and 
 a switching circuit coupled between the first and second voltage supply nodes, and suitable for providing a current path between the first and second voltage supply nodes during a data output disable period, wherein the current path between the first and second voltage supply nodes is not provided during the data output enable period. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the switching circuit electrically separates the first voltage supply node from the second voltage supply node during the data output enable period, and electrically couples the first voltage supply node to the second voltage supply node during the data output disable period. 
     
     
       3. The semiconductor device of  claim 1 , further comprising:
 a first variable resistance element coupled between a first voltage supply terminal and the first voltage supply node; and 
 a second variable resistance element coupled between a second voltage supply terminal and the second voltage supply node. 
 
     
     
       4. The semiconductor device of  claim 3 ,
 wherein the first voltage supply terminal supplies a high voltage having a constant voltage level during the data output enable period and the data output disable period, 
 wherein the second voltage supply terminal supplies a low voltage having a constant voltage level during the data output enable period and the data output disable period, 
 wherein at least one of the first and second variable resistance elements has a first resistance value during the data output enable period and has a second resistance value larger than the first resistance value, during the data output disable period. 
 
     
     
       5. The semiconductor device of  claim 1 , wherein the transmission circuit includes:
 a first current path coupled between the first and second voltage supply nodes; and 
 a second current path coupled between the first and second voltage supply nodes. 
 
     
     
       6. The semiconductor device of  claim 5 , wherein a resistance value of the current path is smaller than a resistance value of the first current path and a resistance value reflected in the second current path, during the data output disable period. 
     
     
       7. The semiconductor device of  claim 5 , wherein the first current path includes first Josephson junctions coupled in series between the first and second voltage supply nodes and first resistance elements, and
 wherein an input pulse signal corresponding to the data value is inputted through an input node between the first Josephson junctions and the first resistance element. 
 
     
     
       8. The semiconductor device of  claim 5 , wherein the second current path includes second Josephson junctions coupled in series between the first and second voltage supply nodes and a second resistance element, and
 wherein the output data signal is outputted through an output node between the second Josephson junctions and the second resistance element. 
 
     
     
       9. The semiconductor device of  claim 1 , wherein the current path between the first and second voltage supply nodes is provided to enhance a level of the output terminal to be settled to a reset level. 
     
     
       10. The semiconductor device of  claim 1 , wherein further comprising:
 a complementary transmission circuit coupled between a third voltage supply node and a fourth voltage supply node, and suitable for outputting a complementary output data signal corresponding to the data value to the output terminal during the data output enable period; and 
 a complementary switching circuit coupled between the third and fourth voltage supply nodes, and suitable for providing a current path between the third and fourth voltage supply nodes during a data output disable period. 
 
     
     
       11. A transmitter comprising:
 a transmission circuit configured to output an output data signal to an output terminal in a superconducting state or a voltage state depending on a data value, during a data output enable period; and 
 a variable resistance element coupled to at least one of first and second supply voltage terminals of the transmission circuit, and configured to have a first resistance value to allow at least a supply voltage having a constant voltage level to be supplied to the transmission circuit during the data output enable period, and a second resistance value to block supplying of the supply voltage to the transmission circuit during a data output disable period. 
 
     
     
       12. The transmitter of  claim 11 , wherein the transmission circuit includes:
 a first current path including first Josephson junctions and a first resistance element coupled in series; and 
 a second current path including second Josephson junctions and a second resistance element coupled in series. 
 
     
     
       13. The transmitter of  claim 11 , wherein the variable resistance element includes:
 a MOS transistor configured to be controlled in response to an output control signal which is activated during the data output enable period and deactivated during the data output disable period. 
 
     
     
       14. A transmitter comprising:
 a transmission circuit configured to output an output data signal to an output terminal in a superconducting state or a voltage state depending on a data value, during a data output enable period; 
 a variable resistance element coupled to at least one of first and second supply voltage terminals, and configured to have a first resistance value to allow at least a supply voltage having constant voltage level to be supplied to the transmission circuit during the data output enable period, and a second resistance value to block supplying of the supply voltage to the transmission circuit during a data output disable period; and 
 a switching circuit configured to selectively provide an additional current path across the transmission circuit during the data output disable period. 
 
     
     
       15. The transmitter of  claim 14 , wherein the transmission circuit includes:
 a first current path including first Josephson junctions and a first resistance element coupled in series; and 
 a second current path including second Josephson junctions and a second resistance element coupled in series. 
 
     
     
       16. The transmitter of  claim 14 , wherein the variable resistance element includes:
 a MOS transistor configured to be controlled in response to an output control signal which is activated during the data output enable period and deactivated during the data output disable period. 
 
     
     
       17. The transmitter of  claim 14 , wherein the switching circuit includes:
 a MOS transistor configured to be controlled in response to a switching control signal which is activated during the data output disable period and deactivated during the data output enable period.