Low drop-out (LDO) voltage regulator circuit

Abstract

A low drop-out (LDO) voltage regulator circuit includes a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to an output node. A current regulation loop senses current flowing through the power transistor and modulates the control signal to cause the power transistor to output a constant current to the output node. A voltage regulation loop senses voltage at the output node and modulates the control signal to cause the power transistor to deliver current to the output node so that an output voltage at the output node is regulated. The current regulation loop includes a bipolar transistor connected to the control terminal of the power transistor, where a base terminal of the bipolar transistor is driven by a signal dependent on a difference between the sensed current flowing through the power transistor and a reference.

What is claimed is: 
     
       1. A low drop-out (LDO) voltage regulator circuit, comprising:
 a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to an output node; 
 a current regulation loop configured to sense current flowing through the power transistor and modulate the control signal to cause the power transistor to output a constant current to the output node; and 
 a voltage regulation loop configured to sense voltage at the output node and modulate the control signal to cause the power transistor to deliver current to the output node so that an output voltage at the output node is regulated; 
 wherein the current regulation loop comprises a control transistor having a first conduction terminal connected to the control terminal of the power transistor and having a control terminal driven by a signal that depends on a difference between the sensed current flowing through the power transistor and a reference; 
 wherein the voltage regulation loop comprises:
 a differential input circuit having a first input configured to receive the voltage sensed at the output node and a second input configured to receive a voltage regulation reference voltage; and 
 a gain circuit having an input coupled to an output of the differential input circuit and an output configured to generate the control signal for application to the control terminal of the power transistor; 
 wherein the gain circuit includes a feedback circuit having a resistor and a capacitor coupled in series, wherein a resistance of the resistor and a capacitance of the capacitor set a zero for canceling a pole at the output node. 
 
 
     
     
       2. The circuit of  claim 1 , wherein the first conduction terminal of the bipolar transistor is an emitter terminal. 
     
     
       3. The circuit of  claim 1 , wherein the power transistor is a MOSFET device. 
     
     
       4. The circuit of  claim 3 , wherein the output terminal of the power transistor MOSFET device is a source terminal. 
     
     
       5. The circuit of  claim 1 , wherein the pole at the output node is set by a load circuit connected to the output node. 
     
     
       6. The circuit of  claim 1 , wherein the resistor is a variable resistor and the capacitor is a variable capacitor. 
     
     
       7. The circuit of  claim 1 , wherein the gain circuit comprises:
 a first gain stage having an input coupled to the output of the differential input circuit; and 
 a second gain stage having an input coupled to an output of the first gain stage; 
 wherein the feedback circuit is coupled between the output of the second gain stage and the input of the second gain stage. 
 
     
     
       8. The circuit of  claim 7 , wherein the second gain stage includes an output drive circuit having a current limiting source circuit. 
     
     
       9. The circuit of  claim 8 , wherein the current limiting source circuit is a current limiting resistor. 
     
     
       10. The circuit of  claim 1 , wherein the control transistor is a bipolar transistor and wherein the power transistor is a MOSFET device. 
     
     
       11. A low drop-out (LDO) voltage regulator circuit, comprising:
 a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to an output node; 
 a current regulation loop configured to sense current flowing through the power transistor and modulate the control signal to cause the power transistor to output a constant current to the output node; and 
 a voltage regulation loop configured to sense voltage at the output node and modulate the control signal to cause the power transistor to deliver current to the output node so that an output voltage at the output node is regulated; 
 wherein the current regulation loop comprises a control transistor having a first conduction terminal connected to the control terminal of the power transistor and having a control terminal driven by a signal that depends on a difference between the sensed current flowing through the power transistor and a reference; 
 wherein the voltage regulation loop comprises:
 a differential input circuit having a first input configured to receive the voltage sensed at the output node and a second input configured to receive a voltage regulation reference voltage; and 
 a gain circuit having an input coupled to an output of the differential input circuit and an output configured to generate the control signal for application to the control terminal of the power transistor; 
 wherein the gain circuit includes a capacitor having a capacitance to set a pole at a frequency that does not exceed a zero at the output node. 
 
 
     
     
       12. The circuit of  claim 11 , wherein the zero at the output node is set by a load circuit connected to the output node. 
     
     
       13. The circuit of  claim 11 , wherein the gain circuit comprises:
 a first gain stage having an input coupled to the output of the differential input circuit; and 
 a second gain stage having an input coupled to an output of the first gain stage; 
 wherein the capacitor has a first terminal connected to the output of the first gain stage and a second terminal connected to a power supply reference voltage. 
 
     
     
       14. The circuit of  claim 13 , wherein the power supply reference voltage is ground. 
     
     
       15. The circuit of  claim 13 , wherein the second gain stage comprises a source-follower transistor. 
     
     
       16. The circuit of  claim 15 , wherein the second gain stage further comprises a current source configured to bias the source-follower transistor. 
     
     
       17. The circuit of  claim 11 , wherein the first conduction terminal of the bipolar transistor is an emitter terminal. 
     
     
       18. The circuit of  claim 11 , wherein the power transistor is a MOSFET device. 
     
     
       19. The circuit of  claim 18 , wherein the output terminal of the power transistor MOSFET device is a source terminal. 
     
     
       20. The circuit of  claim 11 , wherein the control transistor is a bipolar transistor and wherein the power transistor is a MOSFET device. 
     
     
       21. A low drop-out (LDO) voltage regulator circuit, comprising:
 a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to an output node; 
 a current regulation loop configured to sense current flowing through the power transistor and modulate the control signal to cause the power transistor to output a constant current to the output node; and 
 a voltage regulation loop configured to sense voltage at the output node and modulate the control signal to cause the power transistor to deliver current to the output node so that an output voltage at the output node is regulated; 
 wherein the current regulation loop comprises a control transistor having a first conduction terminal connected to the control terminal of the power transistor and having a control terminal driven by a signal that depends on a difference between the sensed current flowing through the power transistor and a reference; 
 wherein the voltage regulation loop comprises:
 a differential input circuit having a first input configured to receive the voltage sensed at the output node and a second input configured to receive a voltage regulation reference voltage; 
 a first amplifier circuit having an input coupled to an output of the differential input circuit, the first amplifier circuit configured to generate a first control signal; 
 a second amplifier circuit having an input coupled to the output of the differential input circuit, the second amplifier circuit configured to generate a second control signal; and 
 an analog multiplexer circuit having a first input configured to receive the first control signal and a second input configured to receive the second control signal, wherein the analog multiplexer circuit selectively passes one of the first and second control signals as the control signal applied to the control terminal of the power transistor in response to a select signal. 
 
 
     
     
       22. The circuit of  claim 21 , wherein the first amplifier circuit comprises:
 a gain circuit having an input coupled to an output of the differential input circuit and an output configured to generate the first control signal; 
 wherein the gain circuit includes a feedback circuit having a resistor and a capacitor coupled in series, wherein a resistance of the resistor and a capacitance of the capacitor set a zero for canceling a pole at the output node. 
 
     
     
       23. The circuit of  claim 22 , wherein the gain circuit comprises:
 a first gain stage having an input coupled to the output of the differential input circuit; and 
 a second gain stage having an input coupled to an output of the first gain stage; 
 wherein the feedback circuit is coupled between the output of the second gain stage and the input of the second gain stage. 
 
     
     
       24. The circuit of  claim 23 , wherein the second gain stage includes an output drive circuit having a current limiting source circuit. 
     
     
       25. The circuit of  claim 21 , wherein the second amplifier circuit comprises:
 a gain circuit having an input coupled to an output of the differential input circuit and an output configured to generate the second control signal; 
 wherein the gain circuit includes a capacitor having a capacitance to set a pole at a frequency that does not exceed a zero at the output node. 
 
     
     
       26. The circuit of  claim 25 , wherein the gain circuit comprises:
 a first gain stage having an input coupled to the output of the differential input circuit; and 
 a second gain stage having an input coupled to an output of the first gain stage; 
 wherein the capacitor has a first terminal connected to the output of the first gain stage and a second terminal connected to a power supply reference voltage. 
 
     
     
       27. The circuit of  claim 26 , wherein the second gain stage comprises a source-follower transistor. 
     
     
       28. The circuit of  claim 21 , wherein the first conduction terminal of the bipolar transistor is an emitter terminal. 
     
     
       29. The circuit of  claim 21 , wherein the power transistor is a MOSFET device. 
     
     
       30. The circuit of  claim 29 , wherein the output terminal of the power transistor MOSFET device is a source terminal. 
     
     
       31. The circuit of  claim 21 , wherein the control transistor is a bipolar transistor and wherein the power transistor is a MOSFET device.