Protection of an integrated circuit

Abstract

A circuit for protecting an integrated circuit against fault injection attacks includes an element including a dielectric which is destroyed, resulting in the occurrence of a short-circuit. The element is connected between two terminals that receive a power supply voltage of the integrated circuit.

What is claimed is: 
     
       1. A protection circuit, comprising:
 a detection circuit configured to detect a fault injection attack against an integrated circuit and to provide an output in response to detecting a fault injection attack; and 
 an element including a dielectric connected between two power supply terminals of the integrated circuit configured to receive a power supply voltage, the dielectric configured to be destroyed in response to the output of the detection circuit to provide a short-circuit between the two terminals. 
 
     
     
       2. The protection circuit of  claim 1 , wherein the element comprises a MOS transistor having conduction terminals connected to the two power supply terminals. 
     
     
       3. The protection circuit of  claim 1 , wherein the dielectric is destroyed through trap-assisted tunneling. 
     
     
       4. The protection circuit of  claim 1 , further comprising at least one fault detector controlling a progressive destruction of the element. 
     
     
       5. The protection circuit of  claim 4 , wherein the detection circuit is configured to provide the output to control application of an electric stress onto the dielectric of the element. 
     
     
       6. The protection circuit of  claim 4 , wherein the detection circuit comprises at least one photon-sensitive element. 
     
     
       7. The protection circuit of  claim 6 , wherein the at least one photon-sensitive element is configured to sense a laser attack of the integrated circuit. 
     
     
       8. A method, comprising:
 detecting fault injection attacks of an integrated circuit; 
 generating an output in response to detecting the fault injection attacks; 
 progressively degrading an element including a dielectric in response to the output, the dielectric being coupled between nodes configured to receive a power supply of the integrated circuit; and 
 providing a short-circuit between the nodes through the dielectric in response to the output. 
 
     
     
       9. The method of  claim 8 , wherein the output defines a duration and intensity of the progressive destruction and is based on a duration and intensity of the fault injection attack. 
     
     
       10. The protection circuit of  claim 1 , further comprising the integrated circuit including:
 a processor; 
 a memory; 
 an input/output interface; 
 a bus coupled to the processor, memory, input/output interface, and the protection circuit. 
 
     
     
       11. The protection circuit of  claim 10 , wherein the protection circuit further comprises a charge pump coupled to the element. 
     
     
       12. A protection circuit, comprising:
 a detection circuit configured to detect a fault injection attack against an integrated circuit, and configured to generate an output in response to detecting the fault injection attack; and 
 a countermeasure element configured to be coupled between first and second nodes configured to receive a power supply voltage of the integrated circuit, the countermeasure element configured to progressively degrade in response to the output from the detection circuit until the countermeasure element provides a short-circuit between the first and second nodes. 
 
     
     
       13. The protection circuit of  claim 12 , wherein the detection circuit generates a plurality of outputs over time in response to a plurality of fault injection attacks, and wherein the plurality of outputs indicate a number of the plurality of the fault injection attacks. 
     
     
       14. The protection circuit of  claim 13 , wherein the plurality of outputs further indicate a duration of the plurality of fault injection attacks. 
     
     
       15. The protection circuit of  claim 12 , wherein the countermeasure element comprises a dielectric. 
     
     
       16. The protection circuit of  claim 15 , wherein the countermeasure element comprises a field effect transistor including a gate oxide, and wherein the dielectric is the gate oxide of the field effect transistor. 
     
     
       17. The protection circuit of  claim 12 , wherein the detection circuit comprises:
 at least one photon sensitive element configured to generate an electronic signal in response to photonic radiation received by the at least one photon sensitive element; and 
 an intensity detection circuit coupled to the at least one photon sensitive element, the intensity detection circuit configured to detect an intensity of the photonic radiation based on the electronic signal, and to compare the intensity to a threshold and generate the output based on the comparison. 
 
     
     
       18. The protection circuit of  claim 17  further comprising a low pass filter coupled between the at least one photon sensitive element and the intensity detection circuit. 
     
     
       19. The protection circuit of  claim 12  further comprising:
 a charge pump; and 
 a switch coupled between the charge pump and the countermeasure element and having a control input coupled to receive the output from the detection circuit. 
 
     
     
       20. The protection circuit of  claim 12  further comprising a charge pump coupled to receive the output from the detection circuit, the charge pump further coupled to the countermeasure element.