Semiconductor circuits, devices and methods

Abstract

A high-voltage sensing device providing full galvanic isolation between a high-voltage domain and a low-voltage domain, wherein the circuit topology of the device resembles that of a Wheatstone bridge, the Wheatstone bridge employing at least one voltage-controlled semiconductor resistor, wherein the circuit also comprises a reference source connected directly to the Wheatstone bridge and the device comprises a number of shielding structures to electrically isolate the high-voltage domain from the low-voltage domain.

The invention claimed is: 
     
       1. A voltage-controlled semiconductor well resistor comprising a gate, a well and a first polycrystalline semiconductor layer forming a shield, wherein the first polycrystalline semiconductor layer has an opening and forms a ring that surrounds a region between the gate and the well, wherein the gate is arranged to control the conductivity in a resistor region of said well resistor. 
     
     
       2. The voltage-controlled semiconductor well resistor according to  claim 1 , wherein the footprint of the gate falls within the footprint of the shield in at least one cross-section taken through the device. 
     
     
       3. The voltage-controlled semiconductor well resistor according to  claim 2 , wherein the footprint is defined as the projection as viewed along a direction perpendicular to a main surface of the gate. 
     
     
       4. The voltage-controlled semiconductor well resistor of  claim 1 , wherein a resistance of said well resistor depends linearly on a voltage applied to said gate. 
     
     
       5. The voltage-controlled semiconductor well resistor according to  claim 1 , wherein said well resistor can withstand up to 2500 V at said gate and has a monotonic change in resistance over the complete input gate voltage range (0 V to 2500 V). 
     
     
       6. The voltage-controlled semiconductor well resistor of  claim 1 , wherein said well is a first well having a first type of doping and is surrounded laterally on all sides by a second well having a second, different type of doping, and wherein said first and second wells extend a substantially same depth into a semiconductor substrate. 
     
     
       7. The voltage-controlled semiconductor well resistor of  claim 1 , wherein said region surrounded by said first polycrystalline semiconductor layer comprises an inter-layer dielectric. 
     
     
       8. The voltage-controlled semiconductor well resistor of  claim 1 , wherein said opening is a substantially rectangular cut-out. 
     
     
       9. The voltage-controlled semiconductor well resistor of  claim 1 , wherein said first polycrystalline semiconductor layer overlaps an outer part of said well, while said opening exposes an inner part of said well, such that an electric field emanating from said gate penetrates said inner part of said well but not said outer part. 
     
     
       10. The voltage-controlled semiconductor well resistor of  claim 1 , wherein said gate overlaps a part of said first polycrystalline semiconductor layer. 
     
     
       11. The voltage-controlled semiconductor well resistor of  claim 10 , wherein said part of said first polycrystalline semiconductor layer overlaps a part of said well. 
     
     
       12. The voltage-controlled semiconductor well resistor of  claim 1 , wherein said shield is arranged relative to said well to substantially prevent parasitic field inversion due to an electric field emanating from said gate. 
     
     
       13. The voltage-controlled semiconductor well resistor of  claim 1 , wherein said first polycrystalline semiconductor layer is connected directly to ground. 
     
     
       14. The voltage-controlled semiconductor well resistor of  claim 1 , wherein said first polycrystalline semiconductor layer is separated from said gate by an inter-layer dielectric. 
     
     
       15. A method for use in manufacturing a voltage-controlled semiconductor well resistor, the method comprising:
 providing a semiconductor substrate; 
 forming a well region within the substrate; 
 forming a polycrystalline semiconductor layer on or above the substrate; 
 forming a dielectric layer on or above the substrate; and 
 forming a gate within a conductive layer above said polycrystalline semiconductor layer, 
 wherein the polycrystalline semiconductor layer forms a shield having an opening and forms a ring surrounding a region between the gate and the well, and 
 wherein the gate is arranged to control the conductivity in a resistor region of said well resistor.