Integrated circuit device and method of manufacturing the same

Abstract

An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.

What is claimed is: 
     
       1. An integrated circuit device comprising:
 a substrate including a first region and a second region; 
 first fin-type active regions protruding from the substrate in the first region, each of the first fin-type active regions including first recesses having first depths from first top surfaces of the first fin-type active regions, respectively; 
 a first device isolation film covering both sidewalls of each of the first fin-type active regions, the first device isolation film having a first minimum thickness in a vertical direction; 
 first source/drain regions filling the first recesses, the first source/drain regions each having a first maximum width at a first level of a first vertical distance from the substrate; 
 second fin-type active regions protruding from the substrate in the second region, each of the second fin-type active regions including second recesses having second depths from second top surfaces of the second fin-type active regions, respectively, the second depths being greater than the first depths, a number of the first fin-type active regions being different from a number of the second fin-type active regions; 
 a second device isolation film covering both sidewalls of each of the second fin-type active regions, the second device isolation film having a second minimum thickness in the vertical direction, the second minimum thickness being greater than the first minimum thickness; and 
 second source/drain regions filling the second recesses, the second source/drain regions each having a second maximum width at a second level of a second vertical distance from the substrate, the second vertical distance being smaller than the first vertical distance, 
 wherein the second maximum width of the second source/drain regions is greater than the first maximum width of the first source/drain regions. 
 
     
     
       2. The integrated circuit device of  claim 1 , wherein a pitch of the first fin-type active regions is different from a pitch of the second fin-type active regions. 
     
     
       3. The integrated circuit device of  claim 1 , wherein the first region is one selected from a logic region and a static random access memory (SRAM) region, and the second region is the other selected from the logic region and the SRAM region. 
     
     
       4. The integrated circuit device of  claim 1 , wherein at least one of the first source/drain regions and the second source/drain regions comprises SiC. 
     
     
       5. The integrated circuit device of  claim 1 , further comprising:
 a first fin insulating spacer disposed on a sidewall of each of the first source/drain regions; and 
 a second fin insulating spacer disposed on a sidewall of each of the second source/drain regions and spaced apart from each of the second-fin type active regions that is adjacent thereto, 
 wherein each of the first source/drain regions laterally extend over the first fin insulating spacer that is adjacent thereto, and each of the second source/drain regions laterally extend over the second fin insulating spacer that is adjacent thereto. 
 
     
     
       6. The integrated circuit device of  claim 1 , further comprising:
 a first fin insulating spacer disposed on a sidewall of each of the first source/drain regions; and 
 a second fin insulating spacer disposed on a sidewall of each of the second source/drain regions, 
 wherein the first fin insulating spacer and the second fin insulating spacer comprise silicon oxycarbonitride (SiOCN) or silicon carbonitride (SiCN). 
 
     
     
       7. The integrated circuit device of  claim 1 , further comprising:
 a first fin insulating spacer disposed on a sidewall of each of the first source/drain regions; 
 a second fin insulating spacer disposed on a sidewall of each of the second source/drain regions; 
 a first gate line on the substrate, the first gate line extending in a direction intersecting the first fin-type active regions in the first region; 
 a first gate insulating spacer disposed on a sidewall of the first gate line; 
 a second gate line on the substrate, the second gate line extending in a direction intersecting the second fin-type active regions in the second region; and 
 a second gate insulating spacer disposed on a sidewall of the second gate line, 
 wherein the first fin insulating spacer and the second fin insulating spacer comprise a first material, and the first gate insulating spacer and the second gate insulating spacer comprise a second material that is the same as the first material. 
 
     
     
       8. The integrated circuit device of  claim 7 , wherein the first gate insulating spacer and the second gate insulating spacer comprise silicon nitride (SiN), silicon oxycarbonitride (SiOCN), or silicon carbonitride (SiCN). 
     
     
       9. The integrated circuit device of  claim 1 , further comprising:
 a first gate line extending in a direction intersecting the first fin-type active regions in the first region; and 
 a second gate line extending in a direction intersecting the second fin-type active regions in the second region, 
 wherein the first gate line and the second gate line comprise titanium nitride (TiN), tantalum nitride (TaN), titanium aluminide (TiA), titanium aluminum carbide (TiAC), titanium aluminum nitride (TiAlN), titanium carbide (TiC), tantalum carbide (TaC), hafnium silicide (HfSi), or a combination thereof. 
 
     
     
       10. An integrated circuit device comprising:
 a substrate including a first region and a second region; 
 first fin-type active regions on the substrate in the first region; 
 second fin-type active regions on the substrate in the second region, a number of the first fin-type active regions being different from a number of the second fin-type active regions; 
 a first device isolation film covering both sidewalls of each of the first fin-type active regions, the first device isolation film having a first minimum thickness in a vertical direction; 
 a second device isolation film covering both sidewalls of each of the second fin-type active regions, the second device isolation film having a second minimum thickness in the vertical direction, the second minimum thickness being greater than the first minimum thickness; 
 a first gate line on the substrate, the first gate line extending in a first direction intersecting the first fin-type active regions in the first region; 
 a second gate line on the substrate, the second gate line extending in a second direction intersecting the second fin-type active regions in the second region; 
 first source/drain regions disposed in first recesses of the first fin-type active regions, the first recesses having first depths from first top surfaces of the first fin-type active regions, respectively; and 
 second source/drain regions disposed in second recesses of the second fin-type active regions, the second recesses having second depths from second top surfaces of the second fin-type active regions, respectively, the second depths being greater than the first depths, 
 wherein each of the first source/drain regions has a first maximum width in the first direction at a first level of a first vertical distance from the substrate, each of the second source/drain regions has a second maximum width in the second direction at a second level of a second vertical distance from the substrate, the second vertical distance is smaller than the first vertical distance, and the second maximum width is greater than the first maximum width. 
 
     
     
       11. The integrated circuit device of  claim 10 , wherein each of the first fin-type active regions has a first width in the first direction, and
 wherein each of the second fin-type active regions has a second width in the second direction, the second width being equal to the first width. 
 
     
     
       12. The integrated circuit device of  claim 10 , wherein the first direction and the second direction are parallel to each other. 
     
     
       13. The integrated circuit device of  claim 10 , wherein a pitch of the first fin-type active regions is different from a pitch of the second fin-type active regions. 
     
     
       14. The integrated circuit device of  claim 10 , wherein at least one of the first source/drain regions and the second source/drain regions comprises SiC. 
     
     
       15. The integrated circuit device of  claim 10 , further comprising:
 a first fin insulating spacer disposed on a sidewall of each of the first source/drain regions; and 
 a second fin insulating spacer disposed on a sidewall of each of the second source/drain regions and spaced apart from each of the second-fin type active regions that is adjacent thereto, 
 wherein the first fin insulating spacer and the second fin insulating spacer comprise silicon oxycarbonitride (SiOCN) or silicon carbonitride (SiCN). 
 
     
     
       16. The integrated circuit device of  claim 10 , further comprising:
 a first gate insulating spacer disposed on a sidewall of the first gate line; and 
 a second gate insulating spacer disposed on a sidewall of the second gate line, 
 wherein the first gate insulating spacer and the second gate insulating spacer comprise silicon nitride (SiN), silicon oxycarbonitride (SiOCN), or silicon carbonitride (SiCN). 
 
     
     
       17. The integrated circuit device of  claim 10 , further comprising:
 first fin insulating spacers disposed on the first device isolation film, the first fin insulating spacers covering the first source/drain regions; and 
 second fin insulating spacers disposed on the second device isolation film, the second fin insulating spacers covering the second source/drain regions. 
 
     
     
       18. The integrated circuit device of  claim 10 , wherein the first gate line and the second gate line comprise titanium nitride (TiN), tantalum nitride (TaN), titanium aluminide (TiA), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), titanium carbide (TiC), tantalum carbide (TaC), hafnium silicide (HfSi), or a combination thereof. 
     
     
       19. An integrated circuit device comprising:
 a substrate including a first region and a second region; 
 first fin-type active regions on the substrate in the first region; 
 second fin-type active regions on the substrate in the second region, a number of the first fin-type active regions is different from a number of the second fin-type active regions; 
 a first device isolation film covering both sidewalls of each of the first fin-type active regions, the first device isolation film having a first minimum thickness in a vertical direction; 
 a second device isolation film covering both sidewalls of each of the second fin-type active regions, the second device isolation film having a second minimum thickness in the vertical direction, the second minimum thickness being greater than the first minimum thickness; 
 a first gate line on the substrate, the first gate line extending in a first direction intersecting the first fin-type active regions; 
 a second gate line on the substrate, the second gate line extending in a second direction intersecting the second fin-type active regions; 
 first source/drain regions disposed in first recesses of the first fin-type active regions, each of the first source/drain regions having a first maximum width in the first direction at a first level of a first vertical distance from the substrate, the first recesses having first depths from first top surfaces of the first fin-type active regions, respectively; 
 second source/drain regions disposed in second recesses of the second fin-type active regions, each of the second source/drain regions having a second maximum width in the second direction at a second level of a second vertical distance from the substrate, the second vertical distance being smaller than the first vertical distance, the second maximum width being greater than the first maximum width, the second recesses having second depths from second top surfaces of the second fin-type active regions, respectively, the second depths being greater than the first depths; 
 a first fin insulating spacer disposed on a sidewall of each of the first source/drain regions; and 
 a second fin insulating spacer disposed on a sidewall of each of the second source/drain regions. 
 
     
     
       20. The integrated circuit device of  claim 19 , wherein
 the first fin insulating spacer and the second fin insulating spacer comprise silicon oxycarbonitride (SiOCN) or silicon carbonitride (SiCN).