Gate driver circuit providing an output voltage that is clamped

Abstract

In one aspect, a gate driver circuit includes a clamp circuit connecting a first node to a second node. The clamp circuit is configured to provide a clamp voltage. The gate driver circuit also includes a first driver connected to the first node and to the second node. The first driver comprising a first input configured to receive the clamp voltage from the clamp circuit. The gate driver circuit further includes a first transistor having a drain connected to the first node, a source connected to a circuit output and a gate connected to an output of the first driver. The first transistor has a gate-to-source voltage and an output voltage of the circuit output does not exceed the clamp voltage less the gate-to-source voltage of the first transistor.

What is claimed is: 
     
       1. A gate driver circuit comprising:
 a clamp circuit connecting a first node to a second node, the clamp circuit configured to provide a clamp voltage to a first driver; 
 the first driver connected to the first node and to the second node, the first driver comprising a first input configured to receive the clamp voltage from the clamp circuit; and 
 a first transistor having a drain connected to the first node, a source connected to a circuit output and a gate connected to an output of the first driver, wherein the first transistor has a gate-to-source voltage, wherein the clamp circuit is not directly connected to the gate of the first transistor, 
 wherein an output voltage of the circuit output does not exceed the clamp voltage less the gate-to-source voltage of the first transistor. 
 
     
     
       2. The gate driver circuit of  claim 1 , further comprising a second transistor having a drain connected to the circuit output and a source connected to the second node. 
     
     
       3. The gate driver circuit of  claim 2 , further comprising a second driver connected to the first node and to the second node,
 wherein the output of the second driver is connected to the gate of the second transistor. 
 
     
     
       4. The gate driver circuit of  claim 2 , wherein the second transistor is an NMOS. 
     
     
       5. The gate driver circuit of  claim 1 , further comprising a Zener diode connecting the first node and the second node. 
     
     
       6. The gate driver circuit of  claim 1 , wherein the first node is configured to connect to a first end of a capacitor and the second node is configured to connect to a second end of the capacitor. 
     
     
       7. The gate driver circuit of  claim 1 , wherein the first transistor is a n-channel metal-oxide-semiconductor field-effect transistor (NMOS). 
     
     
       8. The gate driver circuit of  claim 1 , wherein the second node is configured to be connected to a load. 
     
     
       9. The gate driver circuit of  claim 8 , wherein the load is a coil. 
     
     
       10. The gate driver circuit of  claim 1 , wherein the gate driver circuit is an integrated circuit. 
     
     
       11. A gate driver circuit comprising:
 a clamp circuit connecting a first node to a second node, the clamp circuit configured to provide a clamp voltage; 
 a first driver connected to the first node and to the second node, the first driver comprising a first input configured to receive the clamp voltage from the clamp circuit; and 
 a first transistor having a drain connected to the first node, a source connected to a circuit output and a gate connected to an output of the first driver, wherein the first transistor has a gate-to-source voltage, 
 wherein an output voltage of the circuit output does not exceed the clamp voltage less the gate-to-source voltage of the first transistor, 
 wherein the circuit output is configured to be connected to a gate of an external transistor. 
 
     
     
       12. The gate driver circuit of  claim 11 , further comprising a second transistor having a drain connected to the circuit output and a source connected to the second node. 
     
     
       13. The gate driver circuit of  claim 12 , further comprising a second driver connected to the first node and to the second node,
 wherein the output of the second driver is connected to the gate of the second transistor. 
 
     
     
       14. The gate driver circuit of  claim 11 , further comprising a Zener diode connecting the first node and the second node. 
     
     
       15. The gate driver circuit of  claim 11 , wherein the first node is configured to connect to a first end of a capacitor and the second node is configured to connect to a second end of the capacitor. 
     
     
       16. The gate driver circuit of  claim 11 , wherein the second node is configured to be connected to a coil. 
     
     
       17. A gate driver circuit comprising:
 a clamp circuit connecting a first node to a second node, the clamp circuit configured to provide a clamp voltage; 
 a first driver connected to the first node and to the second node, the first driver comprising a first input configured to receive the clamp voltage from the clamp circuit; and 
 a first transistor having a drain connected to the first node, a source connected to a circuit output and a gate connected to an output of the first driver, wherein the first transistor has a gate-to-source voltage, 
 wherein an output voltage of the circuit output does not exceed the clamp voltage less the gate-to-source voltage of the first transistor, 
 wherein the clamp circuit comprises:
 a current source connected to the first node; and 
 a Zener diode having an anode connected to the second node and a cathode connected to the current source at a third node, 
 wherein the third node provides the clamp voltage. 
 
 
     
     
       18. The gate driver circuit of  claim 17 , further comprising a second transistor having a drain connected to the circuit output and a source connected to the second node. 
     
     
       19. The gate driver circuit of  claim 18 , further comprising a second driver connected to the first node and to the second node,
 wherein the output of the second driver is connected to the gate of the second transistor. 
 
     
     
       20. The gate driver circuit of  claim 17 , further comprising a Zener diode connecting the first node and the second node. 
     
     
       21. The gate driver circuit of  claim 17 , wherein the first node is configured to connect to a first end of a capacitor and the second node is configured to connect to a second end of the capacitor. 
     
     
       22. The gate driver circuit of  claim 17 , wherein the second node is configured to be connected to a coil. 
     
     
       23. A gate driver circuit comprising:
 a clamp circuit connecting a first node to a second node, the clamp circuit configured to provide a clamp voltage; 
 a first driver connected to the first node and to the second node, the first driver comprising a first input configured to receive the clamp voltage from the clamp circuit; and 
 a first transistor having a drain connected to the first node, a source connected to a circuit output and a gate connected to an output of the first driver, wherein the first transistor has a gate-to-source voltage, 
 wherein an output voltage of the circuit output does not exceed the clamp voltage less the gate-to-source voltage of the first transistor, 
 wherein the clamp circuit comprises:
 a second transistor; and 
 a first resistor connected to a drain of the second transistor at a third node, 
 wherein the third node provides the clamp voltage. 
 
 
     
     
       24. The gate driver circuit of  claim 23 , wherein the clamp circuit further comprises:
 a third transistor having a gate connected to the gate of the second transistor, a source connected to the first node, and a drain connected to the gate of the second transistor; 
 a fourth transistor having a drain connected to the drain of the third transistor and a gate connected to a first power supply; 
 a fifth transistor having a drain connected to a source of the fourth transistor; 
 a second resistor connected to ground; and 
 an amplifier having a first input connected to the second resistor, a second input connected to a second power supply and an output connected to a gate of the fifth transistor. 
 
     
     
       25. The gate driver circuit of  claim 24 , wherein the second transistor and the third transistor are each a p-channel metal-oxide-semiconductor field-effect transistor (PMOS). 
     
     
       26. The gate driver circuit of  claim 25 , wherein the fourth transistor and the fifth transistor are each a n-channel metal-oxide-semiconductor field-effect transistor (NMOS). 
     
     
       27. The gate driver circuit of  claim 23 , further comprising a second transistor having a drain connected to the circuit output and a source connected to the second node. 
     
     
       28. The gate driver circuit of  claim 27 , further comprising a second driver connected to the first node and to the second node,
 wherein the output of the second driver is connected to the gate of the second transistor. 
 
     
     
       29. The gate driver circuit of  claim 23 , further comprising a Zener diode connecting the first node and the second node. 
     
     
       30. The gate driver circuit of  claim 23 , wherein the first node is configured to connect to a first end of a capacitor and the second node is configured to connect to a second end of the capacitor. 
     
     
       31. The gate driver circuit of  claim 23 , wherein the second node is configured to be connected to a coil. 
     
     
       32. An integrated circuit (IC) comprising:
 a clamp circuit connected a first node to a second node, the clamp circuit configured to provide a clamp voltage to a first driver; 
 the first driver connected to the first node and to the second node, the first driver comprising a first input configured to receive the clamp voltage from the clamp circuit; 
 a first transistor having a drain connected to the first node, a source connected to a circuit output and a gate connected to an output of the first driver, wherein the first transistor has a gate-to-source voltage, wherein the clamp circuit is not directly connected to the gate of the first transistor; 
 a second transistor having a drain connected to the circuit output and a source connected to the second node; 
 a second driver connected to the first node and to the second node, the second driver having an output connected to the gate of the second transistor; and 
 a clamp connecting the first node and the second node, 
 wherein an output voltage of the circuit output does not exceed the clamp voltage less the gate-to-source voltage of the first transistor. 
 
     
     
       33. An integrated circuit (IC) comprising:
 a clamp circuit connected a first node to a second node, the clamp circuit configured to provide voltage; 
 a first driver connected to the first node and to the second node, the first driver comprising a first input configured to receive the clamp voltage from the clamp circuit; 
 a first transistor having a drain connected to the first node, a source connected to a circuit output and a gate connected to an output of the first driver, wherein the first transistor has a gate-to-source voltage; 
 a second transistor having a drain connected to the circuit output and a source connected to the second node; 
 a second driver connected to the first node and to the second node, the second driver having an output connected to the gate of the second transistor; and 
 a clamp connecting the first node and the second node, 
 wherein an output voltage of the circuit output does not exceed the clamp voltage less the gate-to-source voltage of the first transistor, 
 wherein the clamp circuit comprises:
 a current source connected to the first node; and 
 a Zener diode having an anode connected to the second node and a cathode connected to the current source at a third node, 
 wherein the third node provides the clamp voltage. 
 
 
     
     
       34. An integrated circuit (IC) comprising:
 a clamp circuit connected a first node to a second node, the clamp circuit configured to provide voltage; 
 a first driver connected to the first node and to the second node, the first driver comprising a first input configured to receive the clamp voltage from the clamp circuit; 
 a first transistor having a drain connected to the first node, a source connected to a circuit output and a gate connected to an output of the first driver, wherein the first transistor has a gate-to-source voltage; 
 a second transistor having a drain connected to the circuit output and a source connected to the second node; 
 a second driver connected to the first node and to the second node, the second driver having an output connected to the gate of the second transistor; and 
 a clamp connecting the first node and the second node, 
 wherein an output voltage of the circuit output does not exceed the clamp voltage less the gate-to-source voltage of the first transistor, 
 wherein the clamp circuit comprises:
 a third transistor; and 
 a first resistor connected to a drain of the third transistor at a third node, 
 
 wherein the third node provides the clamp voltage. 
 
     
     
       35. The IC of  claim 34 , wherein the clamp circuit further comprises:
 a fourth transistor having a gate connected to a gate of the third transistor, a source connected to the first node, and a drain connected to the gate of the fourth transistor; 
 a fifth transistor having a drain connected to a source of the fourth transistor and a gate connected to a first power supply; 
 a sixth transistor having a drain connected to a source of the fifth transistor; 
 a second resistor connected to ground; and 
 an amplifier having a first input connected to the second resistor, a second input connected to a second power supply and an output connected to a gate of the sixth transistor. 
 
     
     
       36. An integrated circuit (IC) comprising:
 a clamp circuit connected a first node to a second node, the clamp circuit configured to provide a clamp voltage; 
 a first driver connected to the first node and to the second node, the first driver comprising a first input configured to receive the clamp voltage from the clamp circuit; 
 a first transistor having a drain connected to the first node, a source connected to a circuit output and a gate connected to an output of the first driver, wherein the first transistor has a gate-to-source voltage; 
 a second transistor having a drain connected to the circuit output and a source connected to the second node; 
 a second driver connected to the first node and to the second node, the second driver having an output connected to the gate of the second transistor; and 
 a clamp connecting the first node and the second node, 
 wherein an output voltage of the circuit output does not exceed the clamp voltage less the gate-to-source voltage of the first transistor, 
 wherein the first node is configured to connect to a first end of a capacitor and the second node is configured to connect to a second end of the capacitor, 
 wherein the circuit output is configured to be connected to a gate of an external transistor.