Battery stack monitoring and balancing circuit

Abstract

A method and apparatus for battery stack monitoring and balancing. In one embodiment the apparatus includes a first low-pass filter (LPF) coupled between a first terminal and a first input node of a circuit that comprises a plurality of input nodes, wherein the first terminal is configured to be coupled to a positive terminal of a battery cell. A second LPF is coupled between the first terminal and a second input node of the circuit. A first circuit is coupled between the first terminal and a second terminal, wherein the first circuit is configured to transmit current between the first and second terminals when activated, and wherein the second terminal is configured to be coupled to a negative terminal of the battery cell. A second circuit is coupled between the second and third input nodes, wherein the second circuit is configured to activate the first circuit in response to the second circuit receiving a control signal.

What is claimed is: 
     
       1. An apparatus comprising:
 a first low-pass filter (LPF) coupled between a first terminal and a first input node of a circuit that comprises a plurality of input nodes, wherein the first terminal is configured to be coupled to a positive terminal of a battery cell; 
 a second LPF coupled between the first terminal and a second input node of the circuit; 
 a first circuit coupled between the first terminal and a second terminal, wherein the first circuit is configured to transmit current between the first and second terminals when activated, and wherein the second terminal is configured to be coupled to a negative terminal of the battery cell; 
 a second circuit coupled between the second and third input nodes, wherein the second circuit is configured to activate the first circuit in response to the second circuit receiving a control signal. 
 
     
     
       2. The apparatus of  claim 1  further comprising:
 a third LPF coupled between a third input node of the circuit and the second terminal; 
 a fourth LPF coupled between a fourth input node of the circuit and the second terminal. 
 
     
     
       3. The apparatus of  claim 2  wherein the circuit comprises:
 an analog-to-digital converter (ADC) comprising a pair of input nodes; 
 a switching circuit comprising a pair output nodes coupled to the pair of input nodes of ADC; 
 wherein the switching circuit is configured to selectively couple two input nodes of the circuit to the pair of input nodes of the ADC, respectively, via the pair of output nodes, respectively; 
 wherein the ADC circuit is configured to convert a voltage between its pair of input nodes into a digital equivalent for subsequent transmission to and processing by a device external to the circuit. 
 
     
     
       4. The apparatus of  claim 2  further comprising:
 a third circuit coupled between the second terminal and a third terminal, wherein third circuit is configured to transmit current between the second and third terminals when activated, wherein the third terminal is configured to be coupled to a negative terminal of another battery cell; 
 a fourth circuit coupled to the third input, wherein the second circuit is configured to activate the third circuit in response to the fourth circuit receiving another control signal. 
 
     
     
       5. The apparatus of  claim 1  further comprising:
 a data processing device configured to compare a predetermined value to a digital representation of a voltage between the first and second input nodes; 
 wherein the data processing device is configured to generate a command in response to determining the predetermined value exceeds the digital representation. 
 
     
     
       6. The apparatus of  claim 2  further comprising:
 a data processing device configured to compare a predetermined value to a digital representation of a voltage between the third and fourth input nodes; 
 wherein the data processing device is configured to generate a command in response to determining the predetermined value exceeds the digital representation. 
 
     
     
       7. The apparatus of  claim 1 :
 wherein the first circuit comprises a P-channel MOSFET coupled between the first and second terminals; 
 wherein the second circuit comprises a N-channel MOSFET coupled between the first and second input nodes. 
 
     
     
       8. The apparatus of  claim 4 :
 wherein the third circuit comprises a N-channel MOSFET coupled between the second and third terminals of the battery cell; 
 wherein the fourth circuit comprises a N-channel MOSFET coupled to the third input node. 
 
     
     
       9. The apparatus of  claim 1  further comprising:
 a balancing resistor coupled between the first terminal and the first circuit; 
 wherein each of the first and second LPFs comprise a resistor and a capacitor; 
 wherein resistance of the balancing resistor is less than a resistance of the LPF resistors.